Age | Commit message (Expand) | Author |
2017-07-24 | soc/intel/common/block: Add max SPI transaction time-out as 5 sec | Barnali Sarkar |
2017-07-24 | google/reef: Configure EN_PP3300_DX_LTE on coral | Patrick Georgi |
2017-07-24 | google/reef: copy gpio.c for coral | Patrick Georgi |
2017-07-24 | nb/intel/i440bx: Add final newline to raminit.c | Martin Roth |
2017-07-24 | mb/lenovo/t430: Disable `usb_always_on` by default in CMOS | Patrick Rudolph |
2017-07-24 | soc/intel/skylake: Use common opregion implementation | Patrick Rudolph |
2017-07-24 | sb/intel/i82801jx: Generate default fadt and madt | Arthur Heymans |
2017-07-24 | Update files with no newline at the end | Martin Roth |
2017-07-24 | Fix files with multiple newlines at the end. | Martin Roth |
2017-07-24 | mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pin | Wisley Chen |
2017-07-23 | sb/intel/i82801jx: Add function to detect s3 resume | Arthur Heymans |
2017-07-23 | sb/intel/i82801jx: Add addition IO resources | Arthur Heymans |
2017-07-23 | asus/p2b-d: Use romstage from asus/p2b-ds. | Keith Hui |
2017-07-23 | asus/p2b-f: Use romstage from asus/p2b-ls. | Keith Hui |
2017-07-23 | 440BX boards: Drop unused #includes from romstage | Keith Hui |
2017-07-23 | asus/p2b-ls: Drop onboard LAN from devicetree.cb | Keith Hui |
2017-07-23 | northbridge/intel/i440bx: Merge RAM init routines | Keith Hui |
2017-07-23 | mainboard/google/{poppy,soraka}: Enable S0ix | Rajat Jain |
2017-07-22 | northbridge/intel/i440bx: Move NB macro to i440bx.h | Keith Hui |
2017-07-22 | soc/intel/cannonlake: Keep variable from going out of scope | Martin Roth |
2017-07-22 | mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} config | Furquan Shaikh |
2017-07-22 | mainboard/google/poppy/variants/soraka: Define separate gpio tables | Furquan Shaikh |
2017-07-21 | arch/arm/armv7: Correct checkpatch errors | Logan Carlson |
2017-07-21 | Revert "soc/intel/cannonlake: Add postcar stage support" | Martin Roth |
2017-07-21 | Revert "soc/intel/cannonlake: Call into FSP siliconinit" | Martin Roth |
2017-07-21 | I82801JX: Add IS_ENABLED around config options | Martin Roth |
2017-07-21 | soc/intel/apollolake: Add pci device id for GLK IGD | Hannah Williams |
2017-07-21 | soc/intel/cannonlake: Call into FSP siliconinit | Lijian Zhao |
2017-07-21 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
2017-07-21 | nb/intel/x4x: Rework programming DQ and DQS DLL timings | Arthur Heymans |
2017-07-21 | nb/intel/pineview/raminit: Refactor timings selection | Arthur Heymans |
2017-07-21 | sb/intel/i82801jx: Add correct PCI ids and change names | Arthur Heymans |
2017-07-21 | sb/intel/i82801jx: Copy i82801ix | Arthur Heymans |
2017-07-21 | soc/intel/skylake: Perform LPC offset read after lockdown operation | Subrata Banik |
2017-07-21 | common/block/fast_spi: Perform SPI offset read after lock down operation | Subrata Banik |
2017-07-21 | soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition | Subrata Banik |
2017-07-21 | soc/intel/apollolake: Bring in delta for GLK SOC | Hannah Williams |
2017-07-20 | soc/intel/cannonlake: Make ramstage relocatable | Lijian Zhao |
2017-07-20 | soc/intel/common/gpio: add helpers for relative pin calcuations | Aaron Durbin |
2017-07-20 | soc/intel/common/gpio: fix gpi_status_get() | Aaron Durbin |
2017-07-20 | soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY` | Nico Huber |
2017-07-20 | soc/intel/skylake/igd: Remove dead quirk from dead code path | Nico Huber |
2017-07-20 | soc/intel/skylake: Fix broken memory info HOB scanning | Nico Huber |
2017-07-20 | x86/lapic/secondary.S: Align stack for _secondary_start | Marshall Dawson |
2017-07-20 | soc/intel/common/smbios: Amend debug message | Nico Huber |
2017-07-20 | intel/common/block/i2c: Fix clock programming of i2c | Naresh G Solanki |
2017-07-20 | siemens/mc_apl1: Activate ECC for DRAM | Mario Scheithauer |
2017-07-20 | siemens/mc_apl1: Include platform.asl | Mario Scheithauer |
2017-07-20 | soc/intel/apollolake: Implement _PIC method into ACPI | Mario Scheithauer |
2017-07-19 | soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit | Lijian Zhao |