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2019-10-27mb/(ich7): Use macro instead of magic numberElyes HAOUAS
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/{device,drivers}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27cbmem.h: Align comment with the reality of implementationsArthur Heymans
cbmem_top() should simply not be called before memory is initialed, in order for the implementation to return something meaningful. Change-Id: I8fe32844af290626a0f91279143fda4d3442680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2019-10-26drivers/intel/fsp2_0: move die() calls to the functionsMichael Niewöhner
Since there are no calls where we wouldn't die(), move die() calls into the fsp_find_* functions. Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-26soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculationMichael Niewöhner
Remove the calculation of the Reserved Intel MMIO Memory size from systemagent and memmap, since it is not needed. The size is used in SA to calculate the space between cbmem_top and TSEG without DPR and Chipset Reserved Memory. Since this will always be equal to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved Memory will get reserved alltogether. By reading the code and pratical testing we figured out that: - TSEG - DPR - reserved - top_of_memory == 0 - TSEG - DPR - reserved == top_of_memory This means the whole block will never reserve anything because it is always 0. Hence the code can be removed for simplification. Tested successfully on X11SSM-F Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-26soc,mb/intel: clean up remaining FSP2.0 socs/boardsMichael Niewöhner
Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: move/rename files after drop of FSP 1.1Michael Niewöhner
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26drivers/intel/fsp1_1: remove orphaned functionalityMichael Niewöhner
Remove orphaned functionality from the FSP1.1 driver that only has been used by skylake, which is now FSP2.0-only. Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner
This drops support for FSP 1.1 in soc/intel/skylake, after all boards have been migrated to FSP 2.0, which is backwards compatible. Any moving of files happens in a follow-up commit to make review easier. Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26mb/intel/saddlebrook: Enable serial port on SIOPraveen Hodagatta Pranesh
Enable saddlebrook board Serial port on SuperIO by selecting DRIVERS_UART_8250IO. TEST=Build, Boot saddlebrook board and verified serial logs. Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-10-26mb/intel/saddlebrook: migrate to FSP 2.0Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25trogdor: Provide initial mainboard supportT Michael Turney
Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-25mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft
- This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25soc/intel: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25src/mainboard: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-25ec/{compal,google,quanta}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/lenovo/x201/smihandler: Remove mainboard_io_trap_handler functionPeter Lemenkov
An io_trap_handler on this board is unused in SMM. Change-Id: Ie922f8f1a10495ae887221735c96807261508041 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus mainboard_io_trap_handlerPeter Lemenkov
These mainboard_io_trap_handler functions do nothing compared to a weak mainboard_io_trap_handler in src/cpu/x86/smm/. Change-Id: I73ebcc6c3f604a075a946503d51881ccc6820dac Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitializationPeter Lemenkov
Remove SMM reinitialization since it's already done in src/ec/lenovo/h8. Untested on a real hardware. See also commit 8953d4a1 with Change-Id I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 ("mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler"). Change-Id: Icc582527db15f3a31cdee8948bc5a190240fdc84 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus SMM initPeter Lemenkov
I does nothing on these boards. It's just a call a local noop function which only prints a debug-level message. Change-Id: Id3fb2e9074db72d9025b95f7d4918417dd488b9e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25arch/acpi.h: Convert MADT APIC type names to all capsHimanshu Sahdev
Convert names to all capital in enum acpi_apic_types. Use of these names in corresponding type assign for I/O APIC Structure. Change-Id: Iab2f6d8f645677734df753f8bf59fde4205ce714 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36197 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25arch/acpi.h: Use the aforementioned typedef acpi_table_headerHimanshu Sahdev
Use already declared typedef and modify the usage accordingly. Change-Id: Icf12ab9059be444fbe252b26e70214b1ef062c72 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36194 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{glados,dragonegg}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{drallion,sarien}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/hatch: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Additionally, this change moves mainboard_ec_init() to mainboard dev->init(). TEST=Verified that GPIOs are configured properly and hatch boots to OS. Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/hatch: Set DSM parameters for HeliosCheng-Yi Chiang
Set VPD keys for DSM parameters in overridetree.cb for Helios. RT1011 driver will load values from VPD and set them to device property. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-25mb/google/hatch: Fix speaker mapping for HeliosCheng-Yi Chiang
The correct mapping for speakers to their names should be: uid 0: Woofer Left uid 1: Woofer Right uid 2: Tweeter Left uid 3: Tweeter Right Also, fix the name to be 4-character. BUG=b:140397934, b:143192767 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. And the speaker mapping is correct. Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394Ronak Kanabar
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24mb/google/hatch/var/akemi: Update DPTF thermal sensor for AkemiPeichao Wang
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature BUG=b:143046086 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com>
2019-10-24soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from KconfigJustin Frodsham
BUG=b:143229128 Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27 Signed-off-by: Justin Frodsham <justin.frodsham@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36281 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24src/include/console: Get rid of unused deprecated POST codesElyes HAOUAS
Change-Id: Id577b7c1421e9ffc3f51e90fcc9330c8f3be9a56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-24mb/google/octopus: Override VBT selection for Dorp/Vortininja/VorticonTony Huang
Add enum for Vorticon sku. Vortininja/Vorticon will load vbt_vortininja.bin Dorp will load vbt_dorp.bin BUG=b:143197918 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU-ID sets to Dorp/Vortininja/Vorticon. Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9 Cq-Depend: chrome-internal:2026287 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-24mb/google/{butterfly,link,parrot}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24src/ec/quanta: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24(acpi) superio.asl: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24ec/google/chromeec/acpi: Drop wrong _ADR objectElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/intel/apollolake/acpi: Drop wrong _ADR objects for gpioElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: I9f55cc033b5672917520b139444bc614462c4a05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24soc/mediatek/mt8183: Add udelay after setting voltagesYu-Ping Wu
The SOC DRAM team suggested to delay at least 1us after setting new voltage in PMIC wrapper so the new value can be effective. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variablesJohnny Lin
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Right now the timer is started after FSP-M. Ideally it should be before FSP-M (to detect memory training error). Tested on OCP Mono Lake. Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24drivers/ipmi: Add IPMI BMC FRB2 watchdog timer supportJohnny Lin
Add a function for initializing and starting FRB2 timer with the provided countdown and action values, and a stop function for stopping the timer. Tested on OCP Monolake. Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap filesWerner Zeh
As fmaptool can now handle the offset computation for every mentioned region in the fmap file on its own there is no need to provide the offset in the fmd file anymore. This patch clears this out so that the files are way more readable now. Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-10-24mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for HeliosCheng-Yi Chiang
Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device properties for RT1011 speaker calibration. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: I1010be15466c5060aa1d73318393853a2515daac Reviewed-on: https://review.coreboot.org/c/coreboot/+/36030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-24drivers/i2c/rt1011: Add a driver for RT1011Cheng-Yi Chiang
RT1011 is a smart amplifier. It needs to know speaker related parameters including speaker resistor value and temperature when the calibration is done in order to run Dynamic Speaker Management (DSM) algorithm on chip. The purpose of DSM is to protect speaker when the volume is large. The calibration data of speaker is stored in VPD in factory. This driver is needed to read data from VPD and write to ACPI _DSD when config CHROMEOS_DSM_CALIB is turned on. Kernel rt1011 codec driver will read these device properties to set up codec accordingly on boot. The reason to prepare these parameters in coreboot is because kernel codec driver expects to read per-device parameters directly from device properties. Another benefit is that other OS can also take these parameters through ACPI _DSD table and take benefit of DSM on RT1011. The kernel driver device properties of RT1011 are documented at linux/Documentation/devicetree/bindings/sound/rt1011.txt It is currently in ASoC maintainer's tree at https://kernel.googlesource.com/pub/scm/linux/kernel/git/broonie/sound/+/for-next/ and hopefully should be merged to mainline kernel in the next merge window. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24google/chromeos: Add a library to get DSM calibration dataCheng-Yi Chiang
On ChromeOS, there will be VPD values for dynamic speaker management (DSM) calibration data. They are resistor calibration values and temperature during calibration. These VPD fields use "dsm_calib_" prefix. Known keys are: "dsm_calib_r0_0" "dsm_calib_r0_1" "dsm_calib_r0_2" "dsm_calib_r0_3" "dsm_calib_temp_0" For now these values are unsigned decimal numbers greater than 0. This library will be used for RT1011 device driver in the patch series. Note that in the future we may encode more values into this VPD field if needed. We retain the flexibility for coreboot device driver or codec driver to decode/parse the VPD values based on the needed use case per-board. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: Ib9579a5cc055f8f438cb30a8acaf250a343db19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24acpi: Drop wrong _ADR objects for PCI host bridgesElyes HAOUAS
Found-by: ACPICA 20191018 Change-Id: I81286d89da933b503f605737f28772bfb08483a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36253 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Improve DRAM calibration logsYu-Ping Wu
- Add macro dramc_err. - Some log levels are changed. - Some messages are improved for readability. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Correct continuation line indentYu-Ping Wu
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/intel/fsp_baytrail: use designware I2C driverUwe Poeche
Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C bus device structure. The internal I2C controllers are now handled by the generic PCI driver approach and generic I2C access is enabled. As orientation for the I2C code the actual solution from soc/intel/apollolake I2C was taken. All the I2C specific parts were removed from lpss.c and have been implemented in the I2C driver. Future merge to soc/intel/common/block/i2c/i2c.c would be possible. With this patch I2C chip devices can now be used in devicetree. TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked. Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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