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When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The BL31 on RK3399 is split into multiple segments... the majority goes
into DRAM, but small parts must be put into SRAM and PMUSRAM. With
CB:31123 only the DRAM part was added to memlayout, so the SRAM parts
will not be correctly marked in bootmem and BL31 loading fails the
selfload check. This patch adds the remaining regions to fix the
problem.
Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
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Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This reverts commit 3afb84a24583f5dee9fb407f11b32253d59392bf.
Reason for revert: This is causing issues with the PCIe link
and the system is unable to enter S0ix. Until it can be fixed
in coreboot revert the change here that is not working properly.
BUG=b:124264120
Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31559
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without newline, if IA32_FEATURE_CONTROL already locked, next
console line will be concatenated. If run on a multiple CPUs,
you get multiple lines concatenated.
Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The setting of these registers are only for i2c pin.
BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui
Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/30974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Old location caused spurious error messages when
called from APs, where timestamp_add_now() should
do nothing.
Moving the test also makes get_us_from_boot() usable
from APs (assuming cache coherency).
Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31524
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.
BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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The default mapping was probably copy-pasted from a random
board and disabled some interrupts (by implicitly clearing
some register bits).
We provide a new default mapping with some reasoning, that
tries to be most compatible (i.e. avoids to use PIRQ E-H
that are not shareable on some boards).
The following functions had their interrupt pin disabled
before:
o SATA 2 (explicitly, no board seems to enable the device)
o PCIe Root Port #4, #6-#8 (probably by accident)
PIRQs used before this change: A-D, F and H. After this
change: A-D.
Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31498
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Variants of Hatch need to accommodate single channel DDR. Also,
removing const modifier as we'll need to set these fields
incrementally now. For the single channel configuration, we set
MemorySpdPtr10 to 0. For the dual channel configuration, we set
MemorySpdPtr10 to MemorySpdPtr00.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31262
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change-Id: I8997910ff003a4d0c97656cb1e9a4342230ac51a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Static scan-build indicates a possible invalid return from function
spi_flash_cmd_erase(). The root cause is because the scan believes it's
possible for offset to be above the end address in the first pass, thus
not setting a value for variable ret. Assign initial value of -1 to
variable ret to make checker happy.
BUG=b:112253891
TEST=build grunt
Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The current implementation was designed for x86_32, so don't
attempt to compile it on x86_64 until it is fixed.
Fixes compilation error on x86_64.
Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add HrP 9560 module device ID (0x02F0) into device/pci_ids.h file.
TEST=HrP module is getting detected during PCI enumeration
Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/31475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Every printk() call already does console_tx_flush()
so there should not be anything in transmit buffer
when we return from console_init().
Change-Id: Iff2927c02d2c8031907620a056782bb014f20162
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31369
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After adjustment on Sarien EVT
Touch Screen CLK (Elan): 389.7 KHz
Touch Screen CLK (Melfas): 377.7 KHz
Touch Pad CLK: 385 KHz
BUG=b:122657195
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
measure by scope with sarien.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d
Reviewed-on: https://review.coreboot.org/c/31476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1.
Update setting GPIO H3 to output and low level.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Follow thermal table (b:123383634 comment#1) for EVT1 tunning.
BUG=b:123383634
TEST=Built and tested on sarien system
Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Create VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change enables mode change as a wake source for S3.
BUG=b:124132058
Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:121354442
TEST=None
Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31424
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update dptf for arcada EVT.
BUG=b:123924662
TEST=Built and tested on arcada system
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5
Reviewed-on: https://review.coreboot.org/c/31331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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We need disable touch screen device on laser SKU ID 6.
BUG=none
TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell):
6, Laser14(clamshell + touch):7) distinguish whether disable touch
screen device.
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f
Reviewed-on: https://review.coreboot.org/c/31428
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Extended BIOS ROM Size field.
Change-Id: Iec35c8c66210f0ddc07a2ca6f976a1f8fc53037d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I4e466614d0a9e8c89f298594a5785af775b22a95
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Change-Id: I362292e95557586e0e24a62a12a9ccc98143ef9c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The moved functions are only about locating and loading
the refcode blobs. Separate them from the actual calls
into the blob. Eventually previous binaryPI blobs should
be unified to share same loader code.
Change-Id: I68885e7f855b195c178e746c8f3f0f49166d0def
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I68a8515adf5b29a080f8c5c5b7a96b28bca74676
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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There are typically two configurable oscillator outputs available on APUs
or FCHs. Convert the enable function to work with either one.
BUG=b:none.
TEST=Build and boot grunt.
Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Replace all instances, where 0 is used by the macro/define
`ACPI_FADT_LEGACY_FREE`.
Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/31289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Define VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix
the device configuration in the devicetree.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change sets default bus speed as I2C_SPEED_FAST instead of
I2C_SPEED_STANDARD when board does not provide any speed. This makes
it similar to all other i2c drivers in coreboot.
BUG=b:124403846
BRANCH=nocturne,atlas
Change-Id: I877d837eea2dfebf78ad7d97a32ee2071500625e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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According to request of comment 35, setting ELAN as the default.
BUG=b:122019253
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945
Reviewed-on: https://review.coreboot.org/c/31430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Eanble Elan touch for sarien EVT build
BUG=b:119763054
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a
Reviewed-on: https://review.coreboot.org/c/31413
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The memory between _car_region_start .. _car_region_end has to
be set up as WB in MTRRs for all the cores executing through
bootblock, verstage and romstage. Otherwise global variables may
fail on AP CPUs.
Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n,
which previously did not boot at all for some cases.
Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26115
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If32fa5970ca7ca634833a0e39da66c1f89ed33fe
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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