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2017-12-09soc/intel/cannonlake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-09mainboard/google/kahlee: Update GPIOsMartin Roth
- The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Add EMMC reset on GPIO 93. - Add EMMC bridge PCIe reset on GPIO 40. - Set device enables to high. - Remove extra SCI comment from GPIO 130. - Set individual device PCIe reset pins to high. - Enable global PCIe reset on GPIO 26. - Mark LPC_CLK1 as unused. - Update net names based on latest schematics. - Set Direction and level/edge correctly for SCIs/SMIs. - Remove SCI for pen detect. - Add comments. BUG=b:70234300, b:69681660, b:69305596 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09mainboard/google/kahlee: Update PCIe port mapMartin Roth
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:70255003 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-08src/mainboard/glkrvp: Turn on CPU fanSrinidhi Kaushik
On GLK EC does not support temperature reads and does not control the fans anymore, OS is responsible fan control through EC. This hack enables running of the fan for boards without External EC. Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-08vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51Ravi Sarawadi
Update FSP header files to match FSP v69_51. UPD updates in FSP v69_51 are: - SGX Epoch - Sub/System Vendor ID - Remove deprecated UPD Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/22391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08mb/intel/glkrvp: Fix CLKRUN gpioShaunak Saha
This patch does not put CLKRUN in IOSTANDBY. Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNViHannah Williams
Add CNVi GPE in _PRW for wake on WLAN from S3 Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08soc/intel/apollolake/acpi/pch_hda: Add _PRW for HD-AHannah Williams
Add GPE in _PRW for wake from S3 for HD-audio controller Change-Id: I6ad289be8c58e48ad0ec9d2ee0894fe16b8f2e1c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08google/fizz: Set BJ max current and voltageDaisuke Nojiri
This patch makes coreboot set the max current and voltage for barrel jack adapters. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-08chromeec: Add command to override charger limitDaisuke Nojiri
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which overrides the max input current and voltage when a barrel jack adapter supplies power. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08cr50: Make EC clear AP_OFF before hibnernateDaisuke Nojiri
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes EC clear AP_OFF flag then hibernate. This is needed to make Chromebox boot when cr50 toggles the EC's reset line after TURN_UPDATE_ON command. BUG=b:69721737 BRANCH=none CQ-DEPEND=CL:802632 TEST=Verify Fizz reboot after cr50 update. Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08device/pciexp_device: Set values numerically instead of as bitmaskPatrick Georgi
As noted on linux-pci, we have a weird way to handling "value" and "scale" fields that are supposed to contain numerical values: we encode them as a bitfield. Instead define the two fields (offset and mask) and use numbers. Another issue, not fixed in this CL, is that we write hard-coded values while these fields really need to contain the max() of acceptable delays of the downstream devices. That way the controller can decide whether or not to enter a deeper power management state. It's noted as a TODO. Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-on: https://review.coreboot.org/22740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08mb/google/reef: provide override GPIO table in coralChris Wang
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings for nasher to save the power consumption when the system in S0ix. Change as below: AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0. AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0. BUG=b:69025557 BRANCH=master TEST=compile/verify the power consumption change from ~150mW to ~100mW on clamshell SKU and from ~200mW to ~100mW for convertible SKU. Change-Id: I9e0674f206426fddb3947273754774b310106334 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision are available in single stage and makes use of local references. TEST=Build and boot cannonlake_rvp to get PCH information as below PCH: device id xxxx (rev xx) is Cannonlake-Y Premium Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/intel/skylake: Clean up bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision available in single stage and make use of local references. TEST=Build and boot soraka/eve Change-Id: I6f7f219536831210750a486ee3b3308d6f285451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22756 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/intel/skylake: Remove pch_enable_dev() from SoCSubrata Banik
PCI resources MMIO space/bus master enabling is handled inside pch_dev_enable_resources() from common device code. Hence no need to have an explicit soc function to do the same. TEST=lspci from kernel console shows same pci device list without and without this patch. Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/amd/stoneyridge: Add RO_REGION_ONLYMarc Jones
We only need the apu firmware in the RO region when building for ChromeOS. Adding it to the RW regions is a waste of space. BUG=b:70027919 TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections. Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mainboard/intel/glkrvp: Change gpio configuration for eSPIBora Guvendik
Skip LPC related gpio configuration if eSPI config option is selected. Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07amd/stoneyridge: Delete early_setup.cRichard Spiegel
All preparation done, early_setup.c now useless. Delete early_setup.c, BUG=b:64033893 TEST=None. Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07google/scarlet: update Kingdisplay kd097d04 timingLin Huang
With the old timing, the hblank time isn't large enough, it may cause display artifacts. So fix it. BUG=b:70160653 TEST=panel work on Scarlet rev2 board Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-07asus/p2b-ls: Disable SuperI/O ACPI logical deviceKeith Hui
This logical device is disabled in OEM BIOS. Disable here to match, since its support is currently incomplete anyway. Change-Id: I5c07136ec6a14a8ee8cb68537a2663b78fc0fa20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07asus/p2b: Align ACPI tables with asus/p2b-lsKeith Hui
Updates ACPI tables with work done for asus/p2b-ls, including super I/O related declarations. Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07asus/p2b-ls: Add ACPI tablesKeith Hui
Add ACPI tables support that will be needed for soft-off and S3 resume in the future. Boot tested for soft-off. Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07sb/intel/i82371eb: Rework ACPI tablesKeith Hui
Rework ACPI tables based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. To be pulled in by DSDTs of mainboards using this southbridge. Disable on-the-fly generation of mainboard _CRS node. It is not working as it should and causes runtime errors when booting Linux. This node to be included in mainboard DSDTs in followup patches. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07kahlee/ec.c: Use new wide IO functionRichard Spiegel
In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 TEST=Build, boot and check serial output, search for "Covered by wideIO xx", which should match earlier message "Range assigned to wide IO xx" generated within modified early_ec_init(). Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge/lpc.c: Use new wide IO functionsRichard Spiegel
Use the new wide IO functions from southbridge.c to simplify code in functions set_child_resource and lpc_enable_childrens_resources. BUG=b:64033893 TEST=Boot to OS, check serial output against previously recorded serial output from an image without all 5 related changes. Change-Id: I8533e8ff766df8a8261298559aace7666487826d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge: Create new wide IO functionsRichard Spiegel
Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 TEST=Just build at this stage, full boot to OS and verify serial output at related change 14fdd03a83. Some extra outputs for testing removed when code was committed. Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07mb/google/poppy/variants/nami: Add support for nami boardFurquan Shaikh
This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy: Add support for DDR4 memoryFurquan Shaikh
This change updates memory SPD handling code in baseboard poppy to allow variants to define either LPDDR3 or DDR4 memory types. In addition to that, it also updates the function to print SPD info considering offsets that might be different across the two memory types. BUG=b:70188937 Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy/variants/nautilus: Fix memory paramsFurquan Shaikh
Until now, nautilus was using the DQ-DQS mappings provided by the baseboard. However, based on schematics, these values are not correct. This change adds DQ-DQS mapping tables for nautilus. BUG=b:70188533 Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22706 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: shkim <sh_.kim@samsung.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/apollolake: add ability to enable eSPIBora Guvendik
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/apollolake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/skylake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot cannonlake rvp. Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/apollolake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/skylake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/common/block: Add Intel common Graphics controller supportSubrata Banik
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07intel/bd82x6x: Fix a small mistake in DIR_ROUTETobias Diedrich
The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07intel/bd82x6x: Add missing IRQs in ACPI PIRQ link devicesTobias Diedrich
pch_pirq_init() sets all PIRQ links to route to irq 11. However in the ACPI data, on half the links irq 11 is missing. The other half is missing irq 10. This fixes a mostly cosmetic issue in the Linux messages: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15) Change-Id: I002147d702cacf54a233196932b30732f6a433b3 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07mainboard/intel/glkrvp: Ignore Audio DMIC IOSSTATESathyanarayana Nujella
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice. So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that clock is ON in S0ix state. BUG=None TEST=put DUT in S0ix, verified DMIC_CLK in scope when wov capture path is ON Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07Revert "soc/intel/skylake: Clean up SoC ASL code."Matt DeVillier
This partially reverts commit a7b97510aeb1652fd0006c9b2d10df6568f37e2e. For the internal eMMC to be used by Windows for installation, the CARD device and _RMV methods are required. Without them, Windows does not see/show the eMMC as a valid installation target. TEST: boot google/chell with Tianocore payload and install Windows 10 to the internal eMMC drive. Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22684 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07amd/stoneyridge: Create new name/IRQ associationRichard Spiegel
Table intr_types[] is hard to maintain, and has unused spaces filled with NULL. A new table format is needed that creates strong association between the APIC register index and the associated IRQ name, is easy to maintain and has no unused space (index) to indicate that a particular register is unused while still indicating which registers are valid. Also, the string that defines the name of associated IRQ should be declared with "#define" in a header, but must be physically initiated in a source file. The "#define" must make a strong association between the used register index and the associated IRQ name. Example: #define INDEX_0X16_NAME "PerMon\t" BUG=b:69868534 TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh Processors definitions for Pci_Intr_Index. Also, check for new output format to confirm write_pci_int_table() is working as desired. There's no test for write_pci_cfg_irqs, as it's not being used by kahlee. Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07security/vboot: Remove unused include of vboot_nvstorage.hRandall Spangler
This include is not needed, and the header file is going away in vboot_reference. So, remove it. BUG=chromium:789276 BRANCH=none TEST=emerge-reef coreboot Change-Id: Ie0b37ae3d2f979f79060a15ca3f7157f49c89785 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Randall Spangler <randall@spanglers.com> Reviewed-on: https://review.coreboot.org/22733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07google/gru: Add SKU ID for ScarletJulius Werner
Scarlet has SKU detection strapping pins now. This patch adds the code to read them. BUG=b:69373077 Change-Id: I8d889a845950923bc7b5be9b79792cf3c8b6b8ad Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22697 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07rockchip/rk3399: Select GENERIC_GPIO_LIB KconfigJulius Werner
This option should've been selected by RK3399 the whole time since the SoC supports the <soc/gpio.h> interface. It wasn't really a big deal until now where I'm trying to use a the base2 read helper, though. Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22744 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/*/*/Kconfig: Remove default MMCONF_BASE_ADDRESS on Sandy BridgeArthur Heymans
Change-Id: I6f0d6d7fefc77fb05cdb629d09de8cb72496a9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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