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2015-03-27ryu: initialize LTE modemBen Chan
BUG=chrome-os-partner:30748 TEST=Verify that LTE modem appears on USB during kernel boots on Ryu. Change-Id: I5b73a632ab827abe9c064a097e04d2c9030f9b46 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 070538e60b384d17e17ba3544881ef642c3f33ba Original-Change-Id: I8ec1f94c9aec5b4895a01cdfd3b86f88cd6bb877 Original-Signed-off-by: Ben Chan <benchan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: refactor cpu startup codeAaron Durbin
In order to more easily bring up the 2nd core refactor the cpu startup logic. A common 32bit_entry.S is compiled both for romstage and ramstage to provide the common 32-bit entry point. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted ryu to the kernel. Also, can get the 2nd core up out of reset. Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5 Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213850 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=test_exception generates a page fault which is handled by the exception handler and execution continues after eret from the exception Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213661 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Initialize exception stackFurquan Shaikh
Initialize the exception stack on stage_entry BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling works fine Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2 Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213673 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add exception stack top addressFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling for ryu works fine Change-Id: Ibeac161428c77718a640aa11361fb8d822b4a343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 131f9fca0995a8d07972a5bc5ec76bfea0f1cb42 Original-Change-Id: I5b109d9eb692b9e4ef4bc1f6cf267420f50764da Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213674 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: use named bus numbers instead of literalsAaron Durbin
Use the bus number enumerations from funit to make the pad names and bus numbers consistent and clearer. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted to kernel. Change-Id: If84ed825537f598c033dcacbcba759e0fe4e90ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4375a8e47f572d618044f65603fb9288832f936 Original-Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213492 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add enums for bus namesAaron Durbin
Instead of requiring the mainboards to know the magic literals for the bus numbers provide an easier name to number to handle all the weird ordering. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted on ryu. Change-Id: I4a90f5f5f3ed1d936e2eee23f4726069adc49cc7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b028e90650384c947a3d0ee84c6d1346a22b22b9 Original-Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213491 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: initialize GICAaron Durbin
This provides are barebones initialization for tegra132 GIC on CPU0. It routes all interrupts to CPU0, moves them all into group 1, and attempts to allow non-secure access for all registers (doesn't appear to be implemented, though). BUG=chrome-os-partner:31449 BRANCH=None TEST=Built and booted past smp init in the kernel. Timers appear to be flowing now since jiffies are updated. Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212795 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: move page tables to trustzone regionAaron Durbin
In order to access secure device register space the cpu needs to have the page tables marked as secure memory. In addition the page tables need to live within secure memory otherwise the accesses default to non-secure. Therefore move the page tables to the trustzone region. Remove the TTB_* config options as well as removing the TTB reservations from coreboot's resource list. BUG=chrome-os-partner:31355 BUG=chrome-os-partner:31356 BRANCH=None CQ-DEPEND=CL:213140 TEST=Built and booted into kernel. Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953 Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213141 Reviewed-on: http://review.coreboot.org/8994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Add pad/funit init for i2c6 (audio codec, etc.)Tom Warren
BUG=none BRANCH=none TEST=built ryu, booted to recovery mode OK Ran TegraShell and could r/w I2C6 regs OK Change-Id: I7dca131ab5bd4dac50891937f792ac70b1bb532f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 29591a97fbb8fc42143ff6c7838c9935834ca516 Original-Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212926 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add special I2C6 initTom Warren
I2C6 has a special mux in the SOR/DC domain, so there's a ton of devices that need to be clocked, SOR unpowergated, and then the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register. BUG=none BRANCH=none TEST=none, built rush/ryu AOK Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35 Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: separate/refactor clock enable/reset codeTom Warren
Added distinct functions for clock_enable and clock_clear_reset, and rewrote clock_enable_clear_reset() to use them. Useful when unpowergating SOR partition, for instance, where we need to enable a bunch of periph clocks, unclamp SOR, then take all of those periphs out of reset. BUG=none BRANCH=none TEST=none, built rush/ryu OK. Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2 Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212916 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: never recover cbmem from romstageAaron Durbin
Tegra132 has 2 different paths for booting and resuming from sleep. The boot path uses the typical bootblock, romstage, and ramstage. However, the resume path is completely orthogonal. cbmem_initialize() attempts to recover the cbmem area, but that functionality should not be used from romstage because tegra132 is by definition in a fresh boot if it is executing romstage. Therefore, use cbmem_initialize_empty() so that cbmem is always initialized from scratch on each boot. BUG=chrome-os-partner:31239 BRANCH=None TEST=Built and ran on ryu. Was able to enter recovery and stay in recovery without entering a reboot loop. Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64 Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211424 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Update SPD with correct geometry and timingsDuncan Laurie
This memory is also x16 and needs slight tweak to tRFCmin in order to be functional. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on EVT unit with this config Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6 Reviewed-on: http://review.coreboot.org/8972 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Add PD MCU ACPI device and unmask host eventShawn Nematbakhsh
Samus has a PD MCU, and should handle PD MCU host events. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Verify that ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214860 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit d0752be013f66313d4218338e62372d0f5975097) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6 Reviewed-on: http://review.coreboot.org/8969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27chromeec: Add ACPI device for PD MCU and handle related EC host eventShawn Nematbakhsh
Add ACPI device for PD MCU, if present. Call Notify routine when the corresponding EC host event is received. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host event, and verify ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214809 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit 226b349e40ed8eacce20d0a8063877382f707c69) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iecff6c06f1b37651ff61e36d6085d397d66f861c Reviewed-on: http://review.coreboot.org/8968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Read and save HSIO version from ME in romstageDuncan Laurie
This can be used to know if HSIO registers need updating in ramstage but it is not possible to query the ME for HSIO version after sending the DRAM-init-done message. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus, check for HSIO version messages in log Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13 Reviewed-on: http://review.coreboot.org/8966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix GPE register addressesDuncan Laurie
This macro is incorrect and should be counting by dword instead of byte. The effects of this were subtle: incorrect events in ELOG and hanging when waking from USB input because PME_B0 was not disabled properly. BUG=chrome-os-partner:31611 BRANCH=none TEST=test wake from suspend with USB keyboard Original-Change-Id: I7caf1d46283071787550a9765703897181774957 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214258 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b Reviewed-on: http://review.coreboot.org/8965 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Changes from 2.2.0 ref codeDuncan Laurie
- The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Updates for EVT boardDuncan Laurie
- Remove NFC GPIOs - Change EC wake to GPIO27 - Enable wake on HOTWORD_DET_L_3V3 - Add new Hynix memory SKU BUG=chrome-os-partner:31549 BRANCH=none TEST=emerge-samus coreboot, cannot fully test until EVT Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213796 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1 Reviewed-on: http://review.coreboot.org/8963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Switch to using broadwell platform ASLDuncan Laurie
Instead of providing a local copy use the chipset provided one. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Original-Change-Id: I60dd9bbeefbf4298511abec54635c515fc9b1621 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9dc8e7ae61f0337aa145b7d99acc23852d1cfc9a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I259be321e01e2047666b4be106dea59a5578d9d3 Reviewed-on: http://review.coreboot.org/8962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add broadwell specific platform ASLDuncan Laurie
This can be shared between mainboards, they are still free to override if needed. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: fixed power gating enable for disabled sata portKane Chen
The original code won't set power gating for disabled port correctly, due to it must be set before Lock BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify bit 24, 26 is set in RCBA(0x3a84) for samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab Original-Reviewed-on: https://chromium-review.googlesource.com/213561 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b Reviewed-on: http://review.coreboot.org/8960 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: sata updates from 2.1.0 ref codeKane Chen
fixed a coding error and sync sata configuration with ref code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213137 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa Reviewed-on: http://review.coreboot.org/8959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix devslp enable to use correct registerDuncan Laurie
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add small delay before Flex Ratio rebootDuncan Laurie
In order to prevent possible TPM lockout due to PLTRST assertion shortly after powering up add a small delay before the reset. This will affect cold power up only, reboot/resume/warmboot will all have the flex ratio locked already so this reset is unneeded. BUG=chrome-os-partner:29859 BRANCH=None TEST=build and boot on samus. I tried unsuccessfully to trigger the TPM lockout, but I was not able to do that consistently without this patch so it is unknown yet whether this is 100% effective. Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e Reviewed-on: http://review.coreboot.org/8957 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix TCO register size and event reportingDuncan Laurie
TCO registers are 16bit not 32bit. Also do not log the TCO reset event in S3 resume path to avoid it being logged when TCO is not actually tripping. BUG=chrome-os-partner:28234 BRANCH=None TEST=manual: 1) build and boot on samus 2) modify kernel command line with nmi_watchdog=0 3) while sleep 1 ; do echo -n V ; done > /dev/watchdog & 4) fg 1 5) ctrl-Z 6) wait for reboot 7) check event log for TCO event 8) check suspend/resume path to ensure no TCO event logged Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211840 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6 Reviewed-on: http://review.coreboot.org/8954 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Enable WLAN wake GPIO in _PRWDuncan Laurie
Add ACPI device for WLAN and enable GPIO 10 as wake source in _PRW. BUG=chrome-os-partner:28234,chrome-os-partner:30671 BRANCH=None TEST=boot on samus, check for WLAN in /proc/acpi/wakeup Original-Change-Id: I09b6eeae5bd88ee9d7e0b7e735ed871e8ae6963a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211820 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c65ce028e64aebffb99648b2c34c4ff0e7c4e70f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If192564ddd10c7fe758a4d7266394a30e7d966d4 Reviewed-on: http://review.coreboot.org/8953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Fix some SPD geometry againDuncan Laurie
I was using the wrong datasheet for these parts. Revert to the previous geometry settings so they work again. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211610 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I52ed3609c9686fef13711578597065ca4e907df4 Reviewed-on: http://review.coreboot.org/8951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Disable CMDPWR on broadwellKane Chen
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Tweak GFXPAUSE settings based on revisionDuncan Laurie
Changes from 2.1.0 reference code release. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210607 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb Reviewed-on: http://review.coreboot.org/8949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Update SPDDuncan Laurie
- geometry was incorrect for 8GB modules, should be x32, so refactor the rest of the geometry to match - some of the timing values were off, calcualte new values from the datasheet BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1 Reviewed-on: http://review.coreboot.org/8948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add config option to disable DSP power gating in D3Duncan Laurie
This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26timer: remove rela_time typeAaron Durbin
Current usage doesn't require rela_time. Remove it. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I25dcc1912f5db903a0523428ed1c0307db088eaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26a13d4c615473407f401af4330199bbfe0dd2b1 Original-Change-Id: I487ea81ffb586110e9a1c3c2629d4af749482177 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219714 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rk3288: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=None, but similar usage tested on tegra132. Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05 Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219713 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26cbfs: support concurrent media channels properlyVadim Bendebury
Coreboot generic CBFS media API does not support multiple media access instances, but it should. With this fix the CBFS context (memory cache for SPI accesses) is shared among all open media access streams. A better memory management scheme might be required, but for now this fix allows to support booting deptcharge and accessing VPD through two independent CBFS media streams. BUG=chrome-os-partner:32152 TEST=no exception is thrown when the second stream is opened Change-Id: I62889089b4832c9e9760ef24ecc517220d8f3ec4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 691f9794805d04beff349f1bc60ac9d7530d7cbf Original-Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Remove CHROMEOS defaultPatrick Georgi
We don't set these by default in upstream. Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26Chrome OS vendorcode: Fix vboot_reference compilationStefan Reinauer
Includes moved into $(CPPFLAGS_*), so add that to VBOOT_CFLAGS. Shift vboot build parameters from the environment to be make parameters, and use $(MAKE) instead of make to fix non-Linux build systems. Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26tegra132: allow mainboards to insert memory regions in address mapAaron Durbin
Depending on the needs of the mainboard certain regions of the address map may need to be adjusted. Allow for that. BUG=chrome-os-partner:31293 BRANCH=None TEST=With ryu patches able to insert a non-cacheable memory region. Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9 Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212161 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: Seed the stack at stage_entryFurquan Shaikh
Seed the stack in order to avoid boot process from complaining false stack overflow. BUG=chrome-os-partner:30824 BRANCH=None TEST=Compiles successfully for rush and stack overflow error fixed in boot flow Change-Id: I5d29d24eb5270d38a35a32171881b1aab8bf32e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e53568e82ad8418c20c2410f0cbc5c444c9917 Original-Change-Id: Ie51e1bcd263e3b886feb2e0e9c7d544f23c3444e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210594 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: Initialize CNTFRQFurquan Shaikh
BUG=chrome-os-partner:31356 BRANCH=None TEST=Kernel boots with the changes required in depthcharge Change-Id: I061305e0ab8f6145c0dc74b2ff958a667ff7276a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff2fc86c1c6e6b592fa3faffd360a3a8c6351a9 Original-Change-Id: If1c5850607174ab0f485ef41d47016056d9832cd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212730 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add I2C6 controller to funit libraryTom Warren
BUG=None BRANCH=None TEST=Built rush and ryu, ran on rush into recovery mode. I2C6 is in the SOR domain, so a lot of further init is needed before it can be used. A follow-on patch will do this. Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46 Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212671 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8940 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable external usb 2.0 portAaron Durbin
BUG=chrome-os-partner:31293 BRANCH=None TEST=Able to get sporadic USB communication in depthcharge on ryu. Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8 Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212333 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add usb initialization support to funitAaron Durbin
Continuing down the path of easing mainboard maintenance provide a way to bring up the USB 2.0 ports through funit. BUG=chrome-os-partner:31251 BRANCH=None TEST=With ryu patch was able to get same sporadic USB communication. Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212332 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Add usb support for rush in corebootFurquan Shaikh
BUG=chrome-os-partner:31293 BRANCH=None TEST=With non-cacheable memory region and dma range addition, booting from usb reaches the same point as mmc. Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211039 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: include what is actually usedAaron Durbin
The clk_rst.h file wasn't including files that had functionality it was using resulting in broken builds if just this file was included. BUG=None BRANCH=None TEST=Built with just this file included -> no more errors. Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27 Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212331 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: provide more robust array bounds checkingAaron Durbin
Make sure the array size matches the number of supported FUNITs. Also remove the FUNIT_NONE enumeration so that there isn't an empty slot in the array at index 0. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built when array wasn't large enough. Compiler threw an error. Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04 Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212330 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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