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2020-01-09soc/intel/common: Drop old forked version of SMBUS supportKyösti Mälkki
Switch to use the more recent version in sb/intel/common. Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/broadwell: Drop old forked version of SMBUS supportKyösti Mälkki
Switch to use the more recent version in sb/intel/common. Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Add smbus_{read/write}_word() variantsKyösti Mälkki
Change-Id: I1a9432c901e7baa545d34c1d0f82212bf59f8e23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38141 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/common: Remove extra call layerKyösti Mälkki
Change-Id: I6987eb58b593e1f2bc6adf91be61bf7b5382440d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09lib/spd_bin,soc/intel/common: Move get_spd_smbus()Kyösti Mälkki
Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS functions. Therefore, get_spd_smbus() currently only works with soc/intel/.../smbuslib.c and can be implemented there locally. This allows removal of <device/early_smbus.h>. Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/common: Sync early SMBUS prototypesKyösti Mälkki
Change-Id: I6b4b5ffd552b9eb4467689c8df85905a1c199bb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38120 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09src/mainboard: remove MMIO macrosIdwer Vollering
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09nb/amd/pi/00730F01/state_machine: Add lost optionsMichał Żygowski
Add back options that were lost on postcar migration. Some of them seem to be required for IOMMU initialization. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09amd/agesa/state_machine: Add BeforeInitLate hooksMichał Żygowski
Add missing BeforeInitLate hooks in order to bring back certain options that were lost on postcar migration. This will also allow to disable CDIT again that caused AmdInitLate error on 00730F01. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09AGESA,binaryPI boards: Declare some IRQ tables staticKyösti Mälkki
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() supportKyösti Mälkki
Move things depending on option_table.h to a separate file. Change-Id: Ib23fcd89bf4efef9072fcaea1d8699145c1f2983 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Remove duplicate cmos_chksum_valid()Kyösti Mälkki
Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38194 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/tigerlake: Update KconfigRavi Sarawadi
Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, RP max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-09acpi: Be more ACPI compliant when generating _UIDPatrick Rudolph
* Add function to generate unique _UID using CRC32 * Add function to write the _UID based on a device's ACPI path ACPI devices that have the same _HID must use different _UID. Linux doesn't care about _UID if it's not used. Windows 10 verifies the ACPI code on boot and BSODs if two devices with the same _HID share the same _UID. Fixes BSOD seen on Windows 10. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09superio/common/ssdt: Make disabled PNP devices ACPI compliantPatrick Rudolph
Always write a _HID, even for disabled PNP devices. Fixes a BSOD on Windows 10. Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09nb/intel/sandybridge: Make MCHBAR arithmetics consistentAngel Pons
Ensure that the operation order is always the same. This results in changes to the binary, but the effective result is the same. Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B optionAaron Durbin
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer being used in the code. There's a runtime check for supporting fast read dual output mode of the spi flash. Remove the references to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B. Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08nb/amd/pi: Fix typosElyes HAOUAS
Change-Id: I79ec3a346edde0a63cf344352e58dfb78556dfd8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38244 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08src/lib: Fix typosElyes HAOUAS
Change-Id: Ia1da6637cfca5ddbd0879ea271bc68bb881b92e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37563 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08src/include: Fix typosElyes HAOUAS
Change-Id: I52302e99708bca2f1e5e45f52cacd42e05a5fbd5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37567 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08soc/intel/tigerlake: Fix PMC configRavi Sarawadi
Fix PMC base address for tigerlake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-08mb/google/hatch: Remove fixed IccMax valuesJamie Chen
Remove fixed IccMax values for all domains. IccMax will be selected by CPU SKU in fill_vr_domain_config function. BUG=b:145094963 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-08soc/intel/cannonlake: Add VR config for CMLJamie Chen
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design. BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly. Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-08soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device IDJamie Chen
This patch adds CML-H 4+2 SA DID into systemagent.c and report platform. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-07drivers/spi/flashconsole: Fix shadowing local variableJohanna Schander
Commit c9b13594eb8d425e54a126b5c10e3f6fbc41528b removed the g_ prefix from global variables, leaving the local "offset" variable shadowing the global one. This commit partially reverts this by renaming one of the occations and converting the flushing logic to work on the global object. Change-Id: I246ebdcfd3b973e6a4aa3c15fc5f32497dcf8398 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-07drivers/pc80/rtc: Refactor some USE_OPTION_TABLEKyösti Mälkki
Change-Id: I3a5004db021af6127de2f058bec9d84a985bae67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Refactor clear_cmos variableKyösti Mälkki
After refactoring it is more a status variable rather than a request. Change-Id: I50b8099a08b556129416cea50f0ce6fafe6c14cc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Remove stub for sanitize_cmos()Kyösti Mälkki
We only have a single call-site for this. Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Remove stub for cmos_post_init()Kyösti Mälkki
We only have a single call-site for this. Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07drivers/pc80/rtc: Clean up some headersKyösti Mälkki
Change-Id: I5b3f1da6581dd80264aaa9618227ac64e1966e8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Clean up some inlined functionsKyösti Mälkki
Change-Id: Ie73797b4e9a09605a0685f0b03cb85e9a3be93ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-07src/mainboard: Fix typoElyes HAOUAS
Change-Id: I8a486ce12d6a5f6de31afd279612dc37d3fffd83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-07nb/agesa/family14: Don't use _HID and _ADRElyes HAOUAS
A device object must contain either a _HID object or an _ADR object, but should not contain both. Change-Id: I727116cbc38fcd264c684da6ce766ea5e854f58c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-07mb/google/kahlee/treeya: Tune VIH and meet specPeichao Wang
According to vendor Bayhub requirement need tune VIH make it meets spec --0x304(6:4) CLK = 3 --0x304(3:0) DAT = 5 BUG=None TEST=build firmware and measure VIH whether meets spec Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I4de9e6cfb37e3b76f7afc206cbe3396b8da2d6dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37458 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07mb/google/kahlee/treeya: tune eDP delay time to 20 msPeichao Wang
tune eDP delay time to 20 ms ensure satisfy panel spec BUG=b:147270512 TEST=verify panel sequences by ODM. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL codeSubrata Banik
List of changes in this patch 1. Remove unused variables 2. Make use of absolute path 3. Define macros and use inside SA ASL 4. Rearrange code in nothbridge.asl to move MCRS object under _CRS Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2020-01-07lib/crc_byte: Add CRC32 implementationPatrick Rudolph
* Add CRC32 using polynomial 0x04C11DB7 + Add macro to caculate CRC of a buffer Change-Id: If98e4e12bb53a6e5123e94e8cdffde1eb3bc4b4b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37753 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07acpigen: Add function to generate unicode namesPatrick Rudolph
The ACPI spec 6.3 chapter 6.1.10 states that _STR has to return a buffer containing UTF-16 characters. Add function to generate Unicode names and use it for _STR. It will replace non-ASCII characters with '?'. Use the introduced function in IPMI driver. Fixes ACPI warning shown in fwts. Change-Id: I16992bd449e3a51f6a8875731cd45a9f43de5c8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37789 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06drives/spi_flash: add spi_flash_cmd_write_page_program()Aaron Durbin
The SPI flashes that support page programming mode had duplicated the logic for writing in every driver. Add spi_flash_cmd_write_page_program() and use the common implementation to reduce code size that comes from duplication. The savings is ~2.5KiB per stage where the spi flash drivers are utilized. Change-Id: Ie6db03fa8ad33789f1d07a718a769e4ca8bffe1d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06soc/intel/cannonlake: Add VR config for CFL, CNL and WHLPatrick Rudolph
Add VR config IccMax, DC and AC loadline defaults and voltage regulator maximum for all CFL, CNL and WHL. This supports mainboards with replaceable CPUs and provides sane defaults for boards that are missing the devicetree overwrite. Remove the default IccMax to make use of the introduced lookup-table. Also change some hex values to decimal. I couldn't find CML datasheet, so those are left out for now. Used Doc #337344 and #338023 Section 7. Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37466 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06soc/intel/dnv: Remove commented out Kconfig optionSubrata Banik
Change-Id: Ibe646bad09dcfe348dcbfec439129b2d22ec4744 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06mb/*/*: Remove unused option_table.h includesKyösti Mälkki
These should have been removed together with read_option(). Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06drivers/pc80/rtc: Swap cmos_write32() parameter orderKyösti Mälkki
Make it consistent with the more used cmos_write(). Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-05vc/amd/pi/00670F00: Fix typo in phony target declarationMarshall Dawson
Correct a copy/paste error for warn_no_agesa. Change-Id: Ife2cca47f1f816f99395b33976d08826c53e3c3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05pci_ids: Correct whitespace for all AMD, ATI, National SemiMarshall Dawson
Convert spaces to tabs to match surrounding definitions and fix alignment for AMD products and prior assets. Change-Id: I37f1b7826afab8e224fb2d411247d77ea32664df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-05sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possibleMichał Żygowski
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 04:34:29 +0000