summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2018-05-16commonlib/cbfs: Make cbfsf_file_type publicPatrick Rudolph
Make cbfsf_file_type public to support detecting the payload type at runtime. To be used by the following commits. Possible payload types are: * simple ELF * FIT Change-Id: I37e9fb06f926dc71b001722a6c3b6205a2f20462 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25859 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16lib/prog_loaders: Store CBFS type in struct progPatrick Rudolph
Store the type of the loaded program after locating the file and add a method to retrieve the type. Will be used to distinguish between SELF and FIT payloads. Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26028 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16vx900: Move to EARLY_CBMEM_INITLubomir Rintel
To calculate the CBMEM address we need to determine the framebuffer size early in the ROMSTAGE. We now do the calculation before cbmem_recovery() and configure the memory controller right away. If the calculation was done from cbmem_top() instead, we'd loose some logging that seems useful, since printk() would recurse to cbmem_top() too with CONSOLE_CBMEM enabled. If we didn't configure the memory controller at this point, we'd need to store the result somewhere else. However, CAR_GLOBAL is not practical at this point, because calling car_get_var() from cbmem_top() would recurse back to cbmem_top(). Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-16mb/google/poppy/variants/nami: Load pantheon VBT binaryIvy Jian
Load pantheon.bin by reading sku-id. BUG=b:78663963 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I66cb43d87363b3e8b1a1498cdae8eeeb8b75219d Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16mb/google/poppy/variants/nami: Enable synaptics touchscreen supportIvy Jian
BUG=b:74595040 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. Booted on Pantheon with S7817 PCBa connected 3. Check touchscreen device is enabled by evtest /dev/input/event4: SYTS7817:00 06CB:7817 Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16Revert "cbfs/payload type: Fix build warning and whitespace in name"Ronald G. Minnich
This reverts commit 717ba748366cda19b7532897a5b8d59fc2cd25d9. This breaks seabios and a few other payloads. This is not ready for use. Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methodsJohn Su
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 TEST=Match the result. Change-Id: I4b593118ca460a59aa49786cb99df417d135112a Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-15soc/intel/apollolake: add rt5682 NHLT supportNaveen Manohar
Add APIs and required parameters for creating Realtek 5682 SSP endpoint in NHLT table. BUG=b:79235534 TEST=check that NHLT table defined is created properly. With the series merged & required driver support in kernel. Verify Headset Audio playback. Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/26057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15ACPI: Set the correct number of arguments in ACPI methodsMartin Roth
These methods had unused arguments and could be corrected by setting the correct number in the method initializer. Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-15mainboard/amd/*: Remove unused arguments from SIOW ACPI methodMartin Roth
Since the SIOW method doesn't use any arguments, don't pass it any, and initialize it as not using any. Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-15superio/ite/it8720f: Implement power controlSamuel Holland
Program the Super I/O to turn the machine on or restore its power state when AC power is restored. Based on code from src/superio/nuvoton/nct5572d/superio.c. Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/25463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15mb/scaleway/tagada: Set DIMM slot information from mainboardJulien Viard de Galbert
This field is not provided by the soc code so add it. TEST=Check the output of 'dmidecode -t memory' Change-Id: I6fdf3520da62336a5c654575ed8d1f33eb4f4dc5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15cbfs/payload type: Fix build warning and whitespace in namePaul Menzel
Currently, adding a payload to CBFS using the build system, the warning below is shown. W: Unknown type 'payload' ignored Update payload type from "simple elf" to "simple_elf" and rename the word "payload" to "simple_elf" in all Makefiles. Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF) Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26240 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15mb/emulation/qemu-q35: Enable user option table supportPaul Menzel
It’s unclear why this option was commented out. Activate the line, and copy the CMOS layout and defaults from qemu-i440fx. TEST=Boot 2.11.1(Debian 1:2.11+dfsg-1ubuntu7) and see that nvramcui works. A changed value doesn’t survive a reboot though. Change-Id: Ieef86f092d323c68a6d2d0cc6c04c395f743a935 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26265 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15mb/google/fizz: Add device index for dual LAN skuDavid Wu
Fix dual LAN sku can't inherit correct MAC from VPD setting. BUG=b:77836343 BRANCH=Fizz TEST=Program the mac address to VPD in shell vpd -s ethernet_mac0=<mac address1> vpd -s ethernet_mac1=<mac address2> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/25587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15drivers/net: Check "ethernet_mac" when the device index is 1David Wu
It is a special case for the Fizz firmware branch, when the device index is 1, it will check "ethernet_mac" first and then "ethernet_mac0". For single NIC: config.device_index = "1", maps to "ethernet_mac" For multiple NICs: config.device_index = "1", maps to "ethernet_mac0" BUG=b:77836343 BRANCH=Fizz TEST=Add device index in device tree && Program the mac address to VPD in shell vpd -s ethernet_mac=<mac address> or vpd -s ethernet-mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/26051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14sb/intel/i82371eb: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-14nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
Braces {} are not necessary for single statement blocks. Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14cbfs_locate: Optionally return file typeRonald G. Minnich
In some cases callers want to know if a file exists and, if so, what its type is. Modify cbfs_locate so that if the pointer is non-NULL, but has the value 0, the type of the file that matches the name will be returned. Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14soc/intel/denverton_ns: Enable common code for CPUJulien Viard de Galbert
Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24927 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14mb/scaleway/tagada: Update gpio configuration to use intelblockJulien Viard de Galbert
Update the gpio configuration structure to the intelblock format. The resulting configuration is functionally similar (even if some bits are not identical). Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25424 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14soc/intel/denverton_ns: port gpio to intelblockJulien Viard de Galbert
The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14soc/intel/denverton_ns + mb: Rename gpio configurationJulien Viard de Galbert
In order to use the shared code in intelblock, this patch renames the denverton specific implementation to not use the same names (for files and types). - rename pad_config to remove conflict with soc/.../intelblocks/gpio.h - rename gpio.c, soc/gpio.h to not conflict with intelblock Note: There is no functional change in this patch. Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24926 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14security/vboot: Remove redundent _verstage/_everstage/_verstage_size symbolsSubrata Banik
All those symbols are part of /include/symbols.h file hence removing from /security/vboot/symbols.h Change-Id: Id968186e28d6b772a1a6bca200a852407324d6e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-14pci: Fix compilation on non x86Patrick Rudolph
* Introduce pci_devfn_t on all arch * Add PCI function prototypes in arch/pci_ops.h * Remove unused pci_config_default() Change-Id: I71d6f82367e907732944ac5dfaabfa77181c5f20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25723 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14superio/nuvoton: Add support for NPCD378Patrick Rudolph
The NPCD378 can be found on at least: * HP Compaq 8200 * HP Compaq 8300 The datasheet is not publicly available, as HP implements lots of custom hardware. Add basic support for it, based on HP Compaq 8200. The first eight LDNs seem to be standard nuvoton compatible, except for LDN4, which is used to control front LED and power in ACPI S3. LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's IOBASE with a size of 0x100 bytes. The HWM consists of 16 pages with each holding 0xff bytes. The pages can be selected by writing the page index to IOBASE + 0xff. TODO: Reverse engineer the HWM to support fan control. WARNING: The remaining LDNs have been guessed and might be wrong! The serial has been tested and is working. Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25384 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14cpu/x86/mp: pass pointers to structures for AP callbacksAaron Durbin
In order to extend the MP callback infrastructure prepare for easier changes by making the AP callback get signalled by a single pointer to a local variable on the signaller's stack. When the APs see the callback they will copy the structure to a local variable and then set the acknowledgement by clearing out the slot. The reading and writing to the slots were implemented using inline assembly which forces a memory access and a compiler barrier. BUG=b:74436746 Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26043 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19876 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19875 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
Also throws in some minor fixes like the wrong conditional for bankmod and using real CAS when programming MCHBAR(0x248). Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
Adds nmode to the sysinfo struct as it is needed later on. Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19872 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
A few values were wrong, but it does not seem to matter all that much. Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19871 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
Since this memory controller supports both DDR2 and DDR3 allow it to decode both while making the dram type mutually exclusive. Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
Some things in programming registers related to dual channel interleaved operation were wrong. This also adds some code that could in the future be used when me is active and claims some memory for its UMA. This also uses some more sensible variable names to clarify at least some of the magic. This fixes memtest86+ failing with some assymetric DIMM configuration. TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM configuration setups (would instantly fail at addresses above 4G on many configurations). Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14agesa/hudson/southbridge: add acpi name reporting for lpcKevin Cody-Little
Add an lpc_acpi_name function to report its namespace as "LIBR" rather than some fallback value which seems to vary. This repair is required for the LPC TPM device to register its presence without blowing up the table and preventing the payload from seeing the SATA device. Before change (but after other similar change to PCI0), the TPM device reported itself as: \_SB.PCI0.LPC0.TPM After change, the TPM device reports as: \_SB.PCI0.LIBR.TPM which is consistent with the tables AGESA generates. Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14agesa/family16kb/northbridge: report acpi namespaceKevin Cody-Little
Add a function domain_acpi_name to return "PCI0", rather than falling back to the parent' device's "\_SB" label. This repair is required for the LPC TPM device to register its presence without blowing up the table and preventing the payload from finding SATA. Before change, the TPM device reported as: \_SB.\_SB.LPC0.TPM After change, the TPM device reports as: \_SB.PCI0.LPC0.TPM A separate change submission will correct "LPC0" as well. Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14timestamp: Increase max number of timestampsRaul E Rangel
I'm increasing the max because when AGESA tracing is enabled it will use over 120 entries. I added some padding to the number incase more probes are added. This only affects ramstage so the extra ram shouldn't matter. BUG=b:64549506 TEST=boot on grunt and ran cbmem -t Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14grunt: use stage cache when waking from S3Raul E Rangel
BUG=b:79154155 TEST=built and tested on grunt 31 entries total: 0:1st timestamp 20,917 900:calling AmdInitReset 87,525 (66,608) 901:back from AmdInitReset 98,318 (10,793) 902:calling AmdInitEarly 99,165 (847) 903:back from AmdInitEarly 139,619 (40,454) 5:start of verified boot 156,301 (16,682) 503:starting to initialize TPM 156,697 (396) 504:finished TPM initialization 186,107 (29,410) 505:starting to verify keyblock/preamble (RSA) 187,316 (1,209) 506:finished verifying keyblock/preamble (RSA) 208,000 (20,684) 507:starting to verify body (load+SHA2+RSA) 208,108 (108) 508:finished loading body (ignore for x86) 273,238 (65,130) 509:finished calculating body hash (SHA2) 290,364 (17,126) 510:finished verifying body signature (RSA) 294,236 (3,872) 511:starting TPM PCR extend 295,071 (835) 512:finished TPM PCR extend 320,512 (25,441) 513:starting locking TPM 320,514 (2) 514:finished locking TPM 332,081 (11,567) 6:end of verified boot 332,083 (2) 13:starting to load romstage 332,187 (104) 4:end of romstage 395,559 (63,372) 10:start of ramstage 395,999 (440) 916:calling AmdS3LateRestore 396,135 (136) 917:back from AmdS3LateRestore 428,066 (31,931) 30:device enumeration 428,087 (21) 40:device configuration 434,640 (6,553) 50:device enable 438,185 (3,545) 60:device initialization 439,565 (1,380) 70:device setup done 453,326 (13,761) 918:calling AmdS3FinalRestore 454,363 (1,037) 919:back from AmdS3FinalRestore 455,520 (1,157) 98:ACPI wake jump 467,541 (12,021) Total Time: 446,624 Change-Id: I326e81d3c987130e258c616c7c66dd82ddc0d942 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14program_loading: make types a mask, make unknown type a non-zeroRonald G. Minnich
This will allow loading of programs that are more than one type, e.g. ramstage type might now be a stage or payload. Further, unknown types of 0 are dangerous, make it a real value. Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13drivers/pc80/tpm: get ioport from pnp recordsKevin Cody-Little
Had 0x2e hardcoded, which is often the SuperIO chip. Instead, pull the port from the PNP tree generated from devicetree.cb, where either 0x4e or 0x2e will be specified. Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13mainboard/asus: Add license headersNoah Glovsky
Change-Id: I71e461b91f981368d4bd13631b868430d1fc5774 Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org> Reviewed-on: https://review.coreboot.org/14530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13mainboard/hp: Add HP Elitebook 8770wxiinc37
This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The laptop must be completely disassembled down to the motherboard to perform the initial flash, subsequent flashes can be done internally via flashrom. There is a simple mod that can be performed to make subsequent external flashes easier in case of a brick, I'll put more information on this on the wiki later. The lack of an MXM structure built in to the firmware causes the GPU to enter a mode with nerfed performance, there is a workaround though, I'll add this to the wiki as well. I have no info on EHCI debugging. Tested and working: - memory: 4G+4G, 4G+4G+4G+4G - Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload with graphics init disabled in coreboot. I allowed SeaBIOS to load the VBIOS from the MXM. - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - VGA - DisplayPort - Audio - Both HDD SATA ports, ODD SATA, eSATA - S3 with SeaBIOS 1.11, SERCON must be disabled - Brightness and volume FN keys - Mute and calculator hotkeys - Status LEDs - Bluetooth Not working: - GRUB2 as payload will freeze. Has something to do with at_keyboard module. The built in keyboard requires this module to function though. - Sleep FN key - WiFi toggle and internet browser hotkeys - S3 fails to resume (restarts) if the laptop is removed from AC power, or gets unplugged and then plugged back in while suspended. Sleep status LEDs remain normal during this process. Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a Signed-off-by: Robert Reeves <xiinc37@gmail.com> Reviewed-on: https://review.coreboot.org/23651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13timestamp: Add timestamps for TPM communicationRaul E Rangel
On grunt these operations combined take a little over 37ms. BUG=b:64549506 TEST=built on grunt 511:starting TPM PCR extend 301,268 (598) 512:finished TPM PCR extend 326,710 (25,442) 513:starting locking TPM 326,716 (6) 514:finished locking TPM 339,517 (12,801) Change-Id: I05cfb3d0f8463f073e329a035484a340546649e1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12superio/ite/it8623e: initialize the PWM fan controllerKevin Cody-Little
Copies the common/env_ctrl support code from the it8728f driver. Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload, and booting userspace without a kexec call. Prior to this change, an error was given during boot: it87 it87.656: Detected broken BIOS defaults, disabling PWM interface After this change, the message is gone, and PWM fan control works through the /sys/class/hwmon interface. Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26224 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filenameFurquan Shaikh
This change adds board-specific implementation of mainboard_vbt_filename which returns "vbt.bin" by default. This is in preparation to allow multiple vbt binaries to be added to single image. More sku_id specific names will be added in follow-up CLs. BUG=b:79396300 Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11purism/librem_bdw: Rename Broadwell baseboard from BDL to BDWYouness Alaoui
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so I'm renaming librem_bdl into librem_bdw and changing the KConfig options accordingly. Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26237 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 04:43:26 +0000