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2015-01-10AMD binaryPI: Drop ramtop via nvramKyösti Mälkki
If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is required too. Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10ACPI: Prepare for HAVE_ACPI_RESUME changesKyösti Mälkki
Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8186 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10Fix mainboard names for daisy and peach_pitDavid Hendricks
This just fixes name members of mainboard_ops for daisy and peach_pit, which were never officially supported but used for development and proof-of-concept. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96 Reviewed-on: http://review.coreboot.org/8184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-10haswell: Fix MRC cache to use CBFSKyösti Mälkki
Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though. Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-10macbook21: Add CST entriesAxel Holewa
Due to the CST entries the machine uses less power running GNU/Linux-libre. This can be seen by monitoring CPU temperature and time left the machine can run on battery. CPU temperature measurements have been done with lm_sensors, battery querying with acpi. Tests have been done before applying this patch and after. In both cases the battery was fully loaded and the machine powered up on battery, without AC. In both tests the machine was idleing for more than 1 hour. Without this patch battery was predicted to last 01:52:30 hours, CPU temperature first measurement showed 38 degrees. After 15 min idle, temperature has reached its maximum value in this test of 61 and 62 degrees (Core 0 and 1). Fan speed begins to increase shortly after 15 min. From its minimal value 1800 rpm it reaches 3100 rpm after 40 min. CPU temperature did not increase any further. After 60 min idle, the battery was predicted to still last 57 min. With this patch battery was predicted to last 02:22:40 hours. That is plus 30 min. CPU temperature begins at 35 degrees. After 15 min temperature has reached 45 degrees; after 30 min it has reached the maximal temperature during this test of about 50 degrees. That is 10 degrees improvement. The fan stayed at minimal speed. After 60 min idle, the battery was predicted to still last 01:22:48 hours; a 25 minute improvement. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/7923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09Primitive memory testDavid Hendricks
This adds a generic primitive memory test. We should look into using tests in src/lib/ramtest.c, but they seem to rely too heavily on x86 asm and this test has been useful on multiple ARM platforms. BUG=none BRANCH=none TEST=builds and runs on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed Original-Reviewed-on: https://chromium-review.googlesource.com/186309 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/lib/Makefile.inc Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b Reviewed-on: http://review.coreboot.org/8150 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09nyan*: I2C: Fix bus clear BC_TERMINATE naming.Tom Warren
In the original fix for the 'Lost arb' we were seeing on Nyan* during reboot stress testing, I had the name of BC_TERMINATE's bit setting wrong. Fix this to use the IMMEDIATE (1) setting. The setting didn't change, just the name. According to Julius this is the optimal setting for bus clear in this instance. Also widened the SCLK_THRESHOLD mask to 8 bits as per spec. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206409 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff Reviewed-on: http://review.coreboot.org/8152 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-01-09tegra124: fix and fine tune the warm boot codeJoseph Lo
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and Coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register successfully Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d Reviewed-on: http://review.coreboot.org/8151 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-01-09AMD binaryPI 00730F01: Switch to per-device ACPIKyösti Mälkki
Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09cpu/amd/pi: Use acpi_is_wakeup()Kyösti Mälkki
Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8171 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09amd/agesa/family12/northbridge.c: Indent (tab) fixEdward O'Callaghan
Trivial; Use tab over space for indent. Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8015 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09tegra: i2c: re-init i2c controller after resetJimmy Zhang
This serves as supplemental patch to CL:197732. After clearing bus, we should also redo controller init (because controller has been reset before bus clear). On the upper layer, upon receiving error return status, it should just retry instead of simply call cpu_reset(). BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Built and tested on nyan and nyan_big. Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202784 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984 Reviewed-on: http://review.coreboot.org/8145 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09elog: Add ELOG_TYPE_BOOT event using fake boot count if necessaryDavid Hendricks
This makes it so that we always log the generic "system boot" event. If boot count support has not been implemented, fake it. BUG=chrome-os-partner:28772 BRANCH=nyan TEST=booted on Big, ran "mosys eventlog list" and saw "System boot" event logged with boot count == 0 Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204525 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351 Reviewed-on: http://review.coreboot.org/8142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Updates from P2 buildDuncan Laurie
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d Reviewed-on: http://review.coreboot.org/8135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09x86: Initialize drivers in SMM context if neededDavid Hendricks
This adds a block in the SMI handler to call init functions for drivers which may be used in SMM. A static variable is used to ensure the init functions are only called once. BUG=chrome-os-partner:29580 BRANCH=mccloud TEST=Built and booted on mccloud, system no longer hangs when pressing power button at the dev mode screen. Also tested on parrot. Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee Original-Reviewed-on: https://chromium-review.googlesource.com/204764 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861 Reviewed-on: http://review.coreboot.org/8134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Enable EC ALS deviceDuncan Laurie
Enable the ACPI Device for the EC ALS. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d Reviewed-on: http://review.coreboot.org/8133 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09chrome ec: Add ACPI Device for ALS if enabledDuncan Laurie
The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f Reviewed-on: http://review.coreboot.org/8132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Updates for P2 boardDuncan Laurie
- RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66 - LTE_POWER_ON connection removed BUG=chrome-os-partner:29502 BRANCH=None TEST=none yet, preparing for new board Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203186 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314 Reviewed-on: http://review.coreboot.org/8131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09storm: Reserve memory from 0x4000_0000-0x414f_ffffDavid Hendricks
This marks the bottom chunk of memory, which is used by various IP blocks, as reserved so that Depthcharge does not attempt to wipe it. BUG=chrome-os-partner:30067 BRANCH=storm TEST=Built and booted for storm, depthcharge shows: Wipe memory regions: [0x00000041500000, 0x00000051000000) [0x000000510006a0, 0x00000053000000) [0x00000054141260, 0x0000007fffd000) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77 Original-Reviewed-on: https://chromium-review.googlesource.com/206516 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a Reviewed-on: http://review.coreboot.org/8149 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: Increase DRAM size to 1024MBDavid Hendricks
BUG=chrome-os-partner:29871 BRANCH=storm TEST=builds and boots (sort of) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366 Original-Reviewed-on: https://chromium-review.googlesource.com/206011 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb Reviewed-on: http://review.coreboot.org/8148 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: USB fixes for proto0Vadim Bendebury
The actual storm device has a single USB interface, which needs to be explicitly turned on using GPIO51. BUG=chrome-os-partner:29871 TEST=verified that depthcharge finds and boots a kernel from USB stick Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205329 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7 Reviewed-on: http://review.coreboot.org/8147 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09spi: Add Spansion flash S25FL128PVadim Bendebury
Storm devices use more recent Spansion flash, add its description to the table of supported devices. BUG=chrome-os-partner:29871 TEST=the updated firmware boots all the way to depthcharge Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205182 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f Reviewed-on: http://review.coreboot.org/8146 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09misc: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. Instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the generic code pieces to use printk() on all non-ROMCC boards. Our two remaining ROMCC boards are fixed up in this commit: bifferos/bifferboard and dmp/vortex86ex. Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8115 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09src/mainboard: Doxygen fixesMartin Roth
- Remove @param command for #define - this isn't valid. - Rename duplicate @section names - All of the renamed @sections have other @section names in the same file. - Remove blank @brief and @param commands - Doxygen seems to REALLY dislike this... - Add a missing @param name. Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8175 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09src/include: Doxygen fixesMartin Roth
- Join doxygen file command with the file description - Give extended file location so doxygen knows which early_sbmus.h the file is. (I don't get this either, but it fixes the warning) Change-Id: Ia91fb1ac1e9687e1a5a5cb5234696b3c24d4cd24 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8174 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09mainboard/packardbell/ms2290/romstage.c: Comment unused funcEdward O'Callaghan
Take unused reverse eng function out of build by wrapping in #if 0. Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8167 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09northbridge/intel/nehalem/raminit.c: Remove redundant functionEdward O'Callaghan
Remove 'read_mchbar8_bypass()' as 'read_mchbar8()' does the same thing and 'read_mchbar8_bypass()' is unused. Change-Id: I0dc2325e6205c38b63e5200c408ece65e4f938dc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8166 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09Drop duplicate API from spi_flash.hStefan Reinauer
This convenience API was never used. Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8108 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09asrock/e350m1, lenovo/x2x0 Kconfig: fix indentationNicolas Reinecke
Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8176 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09macbook21 lenovo/xx: Fix inw() in SMI handlersKyösti Mälkki
Missing base may have enabled SMI for all GPI inputs. Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8169 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-08northbridg/via/vx900: Doxygen fixesMartin Roth
- @todo has to be lowercase for doxygen - Fix some parameters that had changed in the code. - The @file entries needed to be more specific. Change-Id: Icdce08735f581609cd25cce41e986c71435368a4 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8154 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-08northbridge/amd: Doxygen fixesMartin Roth
- Add missing parameter names in several files - remove parameter types in several files - remove lines from doxygen documentation. These should be outside the doxygen comments. - Some of the comments shouldn't have been doxygen style. Turn these into regular non-doxygen comments. Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8153 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-07northbridge/amd/agesa/family1{4,5}: Remove cruft from dimmSpd.cEdward O'Callaghan
Remove useless comment pretaining to abusing pragma's for old GCC/GDB interaction issues. Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8017 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-07CBMEM: Rename utility fileKyösti Mälkki
This file will have CBMEM init hooks API one day. Change-Id: I0c31495d4217a5eb235b13e6d8e8c99a87a3b840 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8031 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06mainboard: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the mainboard code to use printk() on all non-ROMCC boards. Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8111 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06cpu: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the cpu code to use printk() on all non-ROMCC boards. Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8114 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06southbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the southbridge code to use printk() on all non-ROMCC boards. Change-Id: I312406257e66bbdc3940e206b5256460559a2c98 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8110 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the northbridge code to use printk() on all non-ROMCC boards. Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7856 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06superio: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the superio code to use printk() on all non-ROMCC boards. Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8113 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06superio/smsc/lpc47n217: Drop dead codeStefan Reinauer
This code is unused, and the same functionality is in superiotool already. Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8112 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06broadwell: Use correct include file for console functionsStefan Reinauer
console_tx_byte() is defined in stream.h, not console.h. This will cause problems later, when untangling more ROMCC and console code. Hence, fix the issue beforehand. Change-Id: If4e04bd6c69b630912414676950157d06c364d74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8121 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06Drop VIA VT8235 southbridgeStefan Reinauer
It's unused. Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7883 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki
This reverts commit 9270553fff23462fcb298f154296319bf3639d15. Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8138 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06AMD platforms: fix callout_entry doxygen errorsMartin Roth
Somewhere along the line, the sb_cfg parameter name was changed to config, but this wasn't carried into the documentation or the function prototypes everywhere. Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8098 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06AMD Mainboards - rd890_cfg.h: fix Doxygen errors.Martin Roth
Doxygen gives an error when processing #defines inside doxygen comments. Normal comments are ignored. The choice for this fix was to make this a standard comment starting with '/*' instead of '/**', or to make the comment not a #define. Change-Id: I97fbbcea6f045d80ec7c0ab5e196d57e5da16d86 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8099 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06doxygen fixes: change @var to @param varMartin Roth
These files were trying to document the parameters, but didn't have the syntax quite right. Change the comments from @varname to @param varname as required by doxygen. Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8100 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06AMD Mainboards - rd890_cfg.c: Fix doxygen warningsMartin Roth
Remove variable types from the param declaration. Change-Id: Ia6a3d36fcf01d7a52bb1a31cfdb47d88bf612d79 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8097 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06doxygen fixes: fix parameter names to match the functionsMartin Roth
The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06Remove AMD's "Release Content" doxygen from coreboot filesMartin Roth
These comments are left over and are not relevent in the coreboot code, but created a new section titled "Release Content" in the doxygen documentation produced by the coreboot code. In an effort to clean up the output, I'm removing these doxygen comments. Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8069 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06drivers/intel/fsp: split the UEFI HOB functions into hob.cMartin Roth
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting and passing information to coreboot. These seem to me like they should be in their own file, so I'm splitting them out of fsp_util.c. I'll be adding a couple more functions in the next patch. These functions should all be compliant to the Hand Off Block spec. Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8065 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 19:42:16 +0000