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2015-04-21romstage_handoff: Fix for changing CBMEM structureDuncan Laurie
Adding a new field to a CBMEM structure does not work if there are systems with older RO that do not have this new field as it means romstage did not prepare the field and ramstage is using it uninitialized. To deal with this instead of adding a new field split the existing s3_resume variable into bytes, using the first byte for the existing s3_resume variable (which is always just 0 or 1) and the second byte for the new varible, which will always be 0 for the old RO and can be set by new RO. BUG=chrome-os-partner:37108 BRANCH=samus TEST=manual testing on samus: 1) ensure that if vboot requests reboot after TPM setup that it still works and the reboot happens after reference code execution. 2) ensure that if RO is older without this change that it does not cause a continuous reboot if newer ramstage is added 3) test that suspend resume still works as expected Reviewed-on: https://chromium-review.googlesource.com/253550 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 1ccb7ee5fc6980ca0f26fa52b385d2cc52f396c9) Change-Id: I6e206b4a3b33b8a31d102d64bd37d34657cf49ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe85678ee788ff939bc8c084829a1b04232c4c6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: If69d0ff9cc3bf596eee8c3a8d6e04951820a26fe Original-Reviewed-on: https://chromium-review.googlesource.com/256114 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron_{brain,danger}: Specify vboot romstage and ramstage indicesDavid Hendricks
This applies the same hack to Danger and Brain as on Rialto which allows us to remove the EC-related sections from their respective flashmaps. BUG=none BRANCH=veyron CQ-DEPEND=CL:255669 TEST=built and booted on Brain w/ depthcharge and mosys changes, was able to read vbnv data from userspace Change-Id: I95715d59a21cd081ac4a3a2216576ede5620f1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4de4273be9ac80ca77a34bc076d1f265fbb94e9f Original-Change-Id: I6c2041e8c17ab157599255a505aaef5e2447a241 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255780 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rk3288: disable rk808 DCDC_UV_ACT_REG restart converter functionhuang lin
if DCDC_UV_ACT_REG setted, when the buck voltage drop to 85%, rk808 will reset this buck, but now when the current consumption large, rk808 may miscarriage of justice this status, so we must disable this function BUG=chrome-os-partner:34834 TEST=Boot from jerry, and do RUNIN test sucess BRANCH=None Change-Id: I08cef73b88d6c2722b389c632c7db29605f4545d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 858c8abc11a824fc3d991a39a49710243f4b1473 Original-Change-Id: I46ebe332c576eebd3386b5042b146a8b57a5c194 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/254496 Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: The ODT function is disabled for LPDDR3jinkun.hong
We found that we should better keep ODT off for LPDDR3 on our boards. BRANCH=veyron BUG=chrome-os-partner:37346 TEST=Boot veyron_speedy normal Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599 Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255381 Reviewed-on: http://review.coreboot.org/9830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: Sync up SDRAM configurationsJulius Werner
This patch adds all SDRAM configurations currently in use for any Veyron board to all boards. In the future we might decide that we want to reuse known good memory from one board on another, and having all of these in there already might help us avoid a firmware rev. We can still differentiate them later if the need ever arises. Not touching Rialto since it already decided to go its own way and replace an existing RAM code with it's own 1GB configuration. Also adjusting the names of the recently added DDR3 4GB configs to fit the existing scheme. Includes changes from "veyron: The ODT function is disabled LPDDR3". BRANCH=veyron BUG=None TEST=Compiled all Veyron boards, booted on Jerry. Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284 Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255665 Reviewed-on: http://review.coreboot.org/9829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rockchip: configure lpddr odt properlyDerek Basehore
The wrong offsets were being used for the GRF_SOC_CON2 register. This also configures odt based on the value of odt in the sdram_params for lpddr systems. BUG=chrome-os-partner:37346 TEST=boot veyron_speedy and veyron_jerry BRANCH=None Change-Id: I13ec3d0df162fe73fabf8af40dd5472e15d6f6af Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 403ab13de17290dc3766bd6f1a03b6effbe58b41 Original-Change-Id: Ic0c18cc7ccf861ef8749e6c950fab9a2802e5f26 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255584 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21cbfs: Print absolute offsets of loaded filesVadim Bendebury
Add the absolute offset value to the CBFS log, to make it easier to understand which particular CBFS section the file is loaded from. BRANCH=storm BUG=none TEST=rebooted a Whirlwind device, observed an empty line before the ramstage section of the log and absolute offsets reported by CBFS. Change-Id: Ifcb79ab386629446b98625a5416dfa5850a105f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ecc4d1df7c51a263230c45ecac5981d53bdd44b1 Original-Change-Id: I5cc727127374d6e55b8ff6f45b250ef97125a8ec Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255120 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9827 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron_jerry: support K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3jinkun.hong
add the K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 inf file, and use ram_id 1110 correspond to K4B8G1646Q-4GB ddr3 use ram_id 1111 correspond to H5TC8G63XXX-4GB ddr3 BUG=None TEST=Boot veyron_jerry normal BRANCH=None Change-Id: I3398516a9f2c2e44c9f5d08d0a3ab6e76b5c6f5f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b8dfc455bb93c2daf567e3b6e39c0a715e44311c Original-Change-Id: I90250cb84eb140f93c4fc655fb3b90584dd515c0 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/255010 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21x86: Allow builds without ACPI tablesLee Leahy
Fix build bug that is referencing vboot_data from vendorcode/google/chromeos/gnvs.c when CONFIG_HAVE_ACPI_TABLES is not set. BRANCH=none BUG=None TEST=Build and run on Glados 1. Checkout updated patches for config, skylake and glados through FspNotify1 2. Verify that mainboard/intel/glados/Kconfig does not select HAVE_ACPI_TABLES 3. emerge-glados coreboot 4. Test passes if build completes successfully Change-Id: Ida5ab8b8dafe30b11dc80dab935e3223d4c760d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1908079360aa065a36956d487eb93142e9c012a1 Original-Change-Id: Icac3845f7e2d1ddffa5f787a640033fba286c13e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/254360 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq806x: i2c: stop transfer as soon as an error is reportedSourabh Banerjee
I2c transfer may consist of multiple segments (for instance write segment to set the register address and then a read segment to read the register value). Transfer should be stopped as soon as a segment processing error has been reported. BRANCH=master BUG=chrome-os-partner:35328 TEST=transfer shall not process the read segment when the write segment fails Change-Id: I85b7b59b376ce33ba3f6d2526be86e9f6585d97b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50cd4d40851b3cea99183c549c47b4486a3deb4a Original-Change-Id: Id65f995d860dd670b289fbdd9eb0ca19a50d7007 Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254494 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq806x: i2c: write function fixed to avoid spurious successSourabh Banerjee
The qup_i2c_write_fifo() made to query QUP_I2C_MASTER_STATUS after QUP transitions into PAUSE state to ensure that it captures the correct status. Handled more error bits. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:35328 TEST=Booted up storm P0.2, verified that the TPM on GSBI1 works. Verified that SUCCESS is not reported when the write FIFO has failed. Change-Id: Ia91638d37b3fa8449630aa2cf932114363b2db78 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75e0d59d2e6ba03182003f22944dbf99ce3eb412 Original-Change-Id: Ic4e8e85686499ce71ad3258b52e687ceff36a1f8 Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254495 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9823 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arch/mips: simplify cache operationsIonela Voinescu
Cache operations are simplified by removing assembly implementation and replacing it with simpler C code. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; caches are properly invalidated; BRANCH=none Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4 Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250792 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rk3288: support single channel ddrjinkun.hong
When using single-channel ddr, DMC channel 1 need to reset dll, otherwise it will lead to pmdomain idle request fails. BUG=chrome-os-partner:35654 BRANCH=veyron TEST=boot rialto Change-Id: Id6b673187c688d238e9a391b3d98720c783e3af4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 927e8426104f8869e139c3f60a04cd49bf726e61 Original-Change-Id: I8be1567040ddb5f2a2b0d06568e517d794ead87a Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250060 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9819 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: Identity map DRAM/SRAMAndrew Bresticker
Using identity_map(), map the DRAM/SRAM regions to themselves (which happens to be using KUSEG on urara). The bootblock (which still runs in KSEG0) sets up the identity mapping in bootblock_mmu_init() so that ROM/RAM stages can be loaded into the KUSEG address range. The stack and pre-RAM CBMEM console also remain in KSEG0 since we don't really care about their physical addresses. Also splitting CBFS cache to pre and post RAM, to allow for larger rambase images. BUG=chrome-os-partner:36258 BRANCH=none TEST=With the rest of coreboot and depthcharge patches applied: - booted urara into the kernel login prompt - from depthcharge CLI tried accessing memory below 0x100000 - observed the exception. Change-Id: If78f1c5c54d3587fe83e25c79698b2e9e41d3309 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9668b440b35805e8ce442be62f67053cedcb205e Original-Change-Id: I187d02fa2ace08b9fb7a333c928e92c54465abc2 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246694 Reviewed-on: http://review.coreboot.org/9816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21mips: Allow memory to be identity mapped in the TLBAndrew Bresticker
Introduce identity_map() function. It takes a memory range and identity maps it entirely in the TLB table, if possible. As a result the virtual and physical address ranges are the same. The function attempts to use as large of a page size as possible for each region in order to conserve TLB entries. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio with the rest of the patches applied. Change-Id: I4d781b04699e069a71c49a0c6ca15c7a6b42a468 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 234d32edfd201019b7a723316a79c932c62ce87e Original-Change-Id: If3e2392b19555cb6dbae8b5559c1b1e53a313637 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246693 Reviewed-on: http://review.coreboot.org/9815 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch
Found that any non-USB3.0 devices connected to type-C ports (displayPort dongles) cause XHCI port to see connection which in turn leads us to enter USB compliance mode. That in turn causes the port to wake the system for a yet-to-be determined reason. Clearing the PORTSC status bits (actually just CSC) seems to remedy the wake. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:35320 TEST=manual, 1. Plug hoho into type-C port on samus and remove 2. powerd_dbus_suspend Device stays asleep. Change-Id: Id3a291579ffca0152a7ef32e37ecae80ca08a82b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0be5cba4916681dceb0372e76d9643e6c7175db5 Original-Change-Id: I1396b9f8013dbbb31286c1d8958af592b3da7475 Original-Reviewed-on: https://chromium-review.googlesource.com/247410 Original-Commit-Queue: Todd Broch <tbroch@chromium.org> Original-Tested-by: Todd Broch <tbroch@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: indent xhci codePatrick Georgi
Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9813 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Skip pre-graphics delay in resume pathDuncan Laurie
If the board is configured with a pre-graphics delay it should be skipped in the resume path. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=measure resume time in dev mode to be same as normal mode Change-Id: I5a4ad5bba9e5316c89f7935d8811759b041429d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44a7167532410fc44ca9df1c91c91aaf541ae49 Original-Change-Id: Ic9f2cda71d8a567f57e863409f0f3fb98ab68bcf Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245116 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9812 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Implement Recovery ButtonRyan Lin
This patch fixes the use of the recovery button, and the value is stored in a SATA controller scratch register. BUG=chrome-os-partner:35241 BRANCH=none TEST=Use recovery button and run firmware_RecoveryButton Change-Id: Ia06f147c7e44d6c4eea2c2e4f502c233c956ee9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34c7ee922a9602b3448a72cd669fd68feeed1bba Original-Change-Id: I1667c7f188b0f87c4bc7caa82f9c977b2b4c0611 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241772 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9811 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21Arrange CBMEM table entries' IDs alphanumericallyVadim Bendebury
This is a no-op change just sorting the CBMEM entries' definitions for easy look up and comparison. BRANCH=storm BUG=none TEST=Booted a storm device, observed the expected CBMEM entries present in the console output. Change-Id: I26365285f20ecb256918277b60e178cd61dc8213 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f140fd8d85ded30d1b89f5d4c64f8b9f31d6b27b Original-Change-Id: Ibcd4f184ef1bade10ad677384f61243da7e3c713 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9810 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-21urara: add config of SPI bus and correct selection of winbond flashIonela Voinescu
Urara uses SPFI interface 1 and Winbond SPI NOR flash. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the fix of the Winbond driver (next patch) the bootblock successfully probes the Windbond device on the FPGA board. Console log below: coreboot-4.0 bootblock Tue Nov 11 07:05:48 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Ia848eac5b4a94bf95297c928b5447463c90d89eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38386715c52526edbe9ad356945849e21799fd94 Original-Change-Id: Ic27b60adc26bf244e7a15b5257e94df4b9d88249 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229030 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21imgtec/pistachio: Add spi_crop_chunk()Patrick Georgi
This was added in upstream but not in Chromium OS where pistachio support was developed. Change-Id: I54f883776f19aa7bd357841731166e92d03145d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-20gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboardDamien Zammit
Board boots to linux. VGA works with rom. Change-Id: I96b73a90c3d88672f0d238f4b735cd2f96ef99bd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/9803 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipsetDamien Zammit
Change-Id: I3375c21d5d4aed30d5641629c44d6a5885efee11 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/9807 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-04-20mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mappingNicolas Reinecke
Tested on T530, T430s. Verified with lspci dump. Change-Id: I45acadb0c55534a67f7ad3e7bd84f4482a4344d7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9451 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20southbrige/intel/bd82x6x: add XHCI overcurrent map configNicolas Reinecke
Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9449 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-20Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UARTPatrick Georgi
Some upstreaming patches missed that, so follow up. Change-Id: I28665c97ac777d8b0b0f909e64b32681ed2b98f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9771 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-20purin: add ns16550 driverDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=booted b0 board. messages printed on console: coreboot-bcf5dc0-dirty bootblock Mon Feb 9 13:33:55 PST 2015 starting... Exception handlers installed. Change-Id: I271ead2f4fe48b809fd311acd5a27a675dce549e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ddff8fb170e775a121150fce065410d2925ad18c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia6e82fa89547d61745c1473f723897dc3c1296ef Original-Reviewed-on: https://chromium-review.googlesource.com/251301 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9765 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20console: copy ns16550 driver from u-bootDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=none Change-Id: I40623e92f290e5c584a451d99071316b6fc35431 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 505720f734da7a4cdfaff8b2531385644141ba83 Original-Change-Id: I655c7065047971ab05a13e90ab911d7464a37552 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251300 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9764 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20chromeos: vboot2: Add TPM PCR extension supportJulius Werner
ChromeOS/vboot devices expect the TPM PCRs 0 and 1 to be extended with digests that attest the chosen boot mode (developer/recovery) and the HWID in a secure way. This patch uses the newly added vboot2 support functions to fetch these digests and store them in the TPM. CQ-DEPEND=CL:244542 BRANCH=veyron BUG=chromium:451609 TEST=Booted Jerry. Confirmed that PCR0 contains the same value as on my vboot1 Blaze and Falco (and PCR1 contains some non-zero hash). Original-Change-Id: I7037b8198c09fccee5440c4c85f0821166784cec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245119 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 8b44e13098cb7493091f2ce6c4ab423f2cbf0177) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I549de8c07353683633fbf73e4ee62ba0ed72ff89 Reviewed-on: http://review.coreboot.org/9706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-20vboot2 workbuf alignment is now 16 bytes, not 8Bill Richardson
BUG=chromium:452179 BRANCH=ToT CQ-DEPEND=CL:243362 TEST=manual emerge-veyron_pinky coreboot Original-Change-Id: Ibcbaea2990e5e06ea7cfaaa5412ef7c1477f5fcc Original-Signed-off-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243380 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 8e5c18eeb21944bdcb064b4491c6781d16ef5608) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I26f6fb67655cb1dfbdcdc48530ef6bfeb1aa692a Reviewed-on: http://review.coreboot.org/9705 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-20rk3288: Disable ramstage compression by defaultJulius Werner
The ramstage is loaded from romstage, so the LZMA scratchpad buffer used to decompress it is part of the romstage BSS in SRAM. On RK3288, SRAM cannot be cached which makes the decompression so slow that it's faster to just load an uncompressed image from SPI. Disable ramstage compression on this SoC to account for that. [pg: implementation avoids restructuring all of Kconfig] BRANCH=None BUG=None TEST=Built for Pinky and Falco, confirmed that the former didn't have COMPRESS_RAMSTAGE in its .config and the latter still did. Measured a speed-up of about 35ms on Pinky. (For some weird reason, the decompression of the payload also takes way longer than on other platforms, although not as long as the ramstage. I have no explanation for that and can't really think of a good way to figure it out... maybe the Cortex-A12 is just terrible at some operation that LZMA uses a lot?) Change-Id: I9f67f7537696ec09496483b16b59a8b73f4cb11b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/234192 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-19southbrige/intel/bd82x6x: XHCI replace magic valuesNicolas Reinecke
Change-Id: I62674ccfb836fb0b02ac562f678cdfa44be98ae3 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9779 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-18riscv: use new-style CBFS header lookupPatrick Georgi
We recently restructured where the CBFS header is stored and how it is looked up, with less magic. The RISC-V port didn't get the memo, so have it follow the pack now. Change-Id: Ic27e3e7f9acd55027e357f2c4beddf960ea02c4d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9795 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-18vboot2: provide path for booting using alternative CBFS instancesVadim Bendebury
When CONFIG_MULTIPLE_CBFS_INSTANCES is enabled, the image is expected to have CBFS instances in rw-a and rw-b sections of the bootrom. This patch adds code which makes sure that CBFS header points at the proper bootrpom section as determined by vboot, and the RW stages load from that section. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=with the rest of the patches in, STORM boots all the way into Linux login prompt. Original-Change-Id: I187e3d3e65d548c672fdf3b42419544d3bd11ea1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237662 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 71ad0bb41b183374a84a5b9fb92c3afd813ceace) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia05cb713981c44da8cb379b72dfbe17fe1f6c5ff Reviewed-on: http://review.coreboot.org/9704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18vboot2: Implement new vb2ex_hwcrypto APIJulius Werner
This patch aligns our verstage code to the new API addition in vboot2. The hardware crypto functions are stubbed out by default and just pretend that all algorithms are unsupported, causing vboot to fall back to the normal software hashing code. These weak symbols can be overridden by individual platform code to provide actual hardware crypto engine support. CQ-DEPEND=CL:236453 BRANCH=None BUG=chrome-os-partner:32987 TEST=Booted Pinky, confirmed vboot falls back to software crypto. Original-Change-Id: Idf6a38febd163aa2bff6e9a0e207213f01ca8324 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236435 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 9b5ee7f575f1aa3b0eb6ef78947ca93a4818f57b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I6f0e19255a9bc5c5cd1767db76f1e47897ef0798 Reviewed-on: http://review.coreboot.org/9703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18vboot: make vboot2_verify_firmware returnDaisuke Nojiri
this allows each board to decide what to do after firmware verification is done. some board needs to return back to the previous stage and let the previous stage kick off the verified stage. this also makes it more visible what is going to happen in the verstage since stage_exit now resides in main(). BUG=none BRANCH=tot TEST=booted cosmos dev board. booted blaze in normal and recovery mode. built for all current boards. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I3cb466cedf2a9c2b0d48fc4b0f73f76d0714c0c7 Original-Reviewed-on: https://chromium-review.googlesource.com/232517 (cherry picked from commit 495704f36aa54ba12231d396376f01289d083f58) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ic20dfd3fa93849befc2b37012a5e0907fe83e8e2 Reviewed-on: http://review.coreboot.org/9702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18ipq806x: initialize UART even when console is not enabledVadim Bendebury
The ipq806x UART is based on the same universal serial port which can be also configured as i2c or SPI. Configuring it is not a trivial task, so in case the kernel wants to use earlyprintk() the port needs to be configured by the firmware. Invoking uart_init() when the console is not enabled causes include file collisions, which would require changes to more than 100 files. Leaving this to another day, rearranging the ipq806x driver to be able to invoke UART initialization function even when serial console is not configured. Also add a check to avoid initialization if UART has been already set up. BRANCH=storm BUG=chrome-os-partner:35364 TEST=verified that storm console is still fully operational when enabled, and that the kernel boots fine to the serial console login prompt even if the firmware console is disabled. Change-Id: Ibbbab875449f2ac2f0d6c504c18faf0da8251ffa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c512d6c1d0c0868137d1213ea84cd4bca58872db Original-Change-Id: I421acba3edf398d960b5058f15d1abb80ebc7660 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240516 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18ipq806x: uart: replace hardware accessorsVadim Bendebury
Originally ported QCA UART driver used hardware accessor macros where both address and data were represented by 32 bit integers. Coreboot uses macros where addresses are represented by pointers, this make the code more robust, as accidental swap between address and data does not go unnoticed. This patch converts ipq806x UART driver to use coreboot accessors. It relies on gcc void pointer arithmetic considering objects pointed at by void pointers to be one byte in size. Also replacing spaces with hard tabs where appropriate. BRANCH=storm BUG=chrome-os-partner:34790 TEST=new code still boots fine on Storm with console output present. Change-Id: I3ded9c338ff241bb1d839994f7296756aad8772d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10616351704ebbcfcf25793ae974b256bc5bd6b0 Original-Change-Id: Ie15e09f9f3ea10a8566b6845219c2e09fed39218 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240514 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Set C9/C10 vccminDuncan Laurie
This is done via a PCODE mailbox write. BUG=chrome-os-partner:37043 BRANCH=broadwell TEST=build and boot on samus Change-Id: I95e8fe3e28eec76d6b5b488a0c770c04f408700e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b90bef7f708b1ce83f6e124f4b38ae51ec6b0597 Original-Change-Id: I95cd4c17db672a53ba05f85ba5fa7bc866af1543 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/252862 Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit ab6b4bddf3365713aa40d194c2dbd3e59985f00d) Original-Reviewed-on: https://chromium-review.googlesource.com/252883 Reviewed-on: http://review.coreboot.org/9783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Disable XHCI compliance mode entryDuncan Laurie
To avoid entries with Type-C alternate mode devices disable compliance mode entry. This needs to be set on both boot and resume. BUG=chrome-os-partner:35320 BRANCH=samus TEST=manual: 1) boot on samus with USB keyboard plugged in -> controller in D0 at boot 2) iotools mmio_read32 0xe12080ec == 0x18010c01 3) suspend and resume 4) iotools mmio_read32 0xe12080ec == 0x18010c01 5) remove USB keyboard -> controller in D3 6) iotools mmio_read32 0xe12080ec == 0xffffffff 7) plug in USB keyboard -> controller in D0 8) iotools mmio_read32 0xe12080ec == 0x18010c01 9) boot with no external USB devices -> controller in D3 at boot 10) iotools mmio_read32 0xe12080ec == 0xffffffff 11) plug in USB keyboard -> controller in D0 12) iotools mmio_read32 0xe12080ec == 0x18010c01 Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059 Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251361 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18panther: Fix pointer related errors in LAN codeFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles and boots to "starting kernel" on panther Change-Id: Ic71aea6d8939a4fa3cd890e2048fff22ea25d186 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b5515bd00b76332748e4181cdf984c98a83993a Original-Change-Id: I2f890871ad7cddaf132a0fa59a93f05c51d0c00e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234982 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18soc/intel/common: Add common reset codeLee Leahy
Move reset support into the Intel common branch. Prevent breaking of existing platforms by using a Kconfig value to select use of the common reset code. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2 Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18soc/intel/common: Add function to protect MRC cacheDuncan Laurie
Add support for applying write protection to the MRC cache region in SPI flash. This is only enabled if there is write protect GPIO that is set, and the flash status register reports that the flash chip is currently write protected. Then it will call out to a SOC specific function that will enable write protection on the RW_MRC_CACHE region of flash. The implementation is not quite as clean as I would like because there is not a common flash protect interface across SOCs so instead it relies on a new Kconfig variable to be set that will indicate a SOC implements the function to protect a region of SPI flash. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus 1) with either WPSW=0 or SRP0=0 the PRR is not applied 2) with both WPSW=1 and SRP0=1 the PRR is applied Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6 Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241170 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18broadwell: add ROM stage pre console init call backWenkai Du
Serial port on ITE 8772 SuperIO must be initialized before console_init is called. So the pre console init callback is added to let mainboard code do proper initialization. Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1 Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227933 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-17cygnus: enable mmuDaisuke Nojiri
this is not only for speed but also preventing the cpu from crashing. the cpu is not happy when cache is cleaned without mmu turned on. BUG=chrome-os-partner:36691 BRANCH=broadcom-firmware TEST=boot purin to romstage. Change-Id: I2445dcc2729798c4fc56fa191cbc8471ef708d08 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e35c925b75213e1d35bf191f22c39aaf1726eeb Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icaf8c506df258edb99413949e6e3089a2b1a91af Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199388 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251306 Reviewed-on: http://review.coreboot.org/9768 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17cygnus: configure memlayoutDaisuke Nojiri
we also pick no RETURN_FROM_VERSTAGE. BUG=none BRANCH=broadcom-firmware TEST=booted b0 board Change-Id: Iddd95f233a614187ae6b26f351a289c23f25742f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 243598925333982b40297adad878c461990d7d70 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I6ab96628cecb84e061777cc85d6d572823f6d63c Original-Reviewed-on: https://chromium-review.googlesource.com/251303 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9767 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17cygnus: add timer functionsDaisuke Nojiri
this implements udelay. BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 sec of delay by stopwatch Change-Id: I833b71fac98a871bff71478221a55e1ca15c13df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 137456e63931052f80247b72f98f958afdba8a27 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ib5e33a19421eae900800fce94e9fd51bc2c665c4 Original-Reviewed-on: https://chromium-review.googlesource.com/251302 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17urara: Define UART used for serial consoleDavid Hendricks
BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara with follow-up patches Change-Id: I0ed55f372e095f6b63a47734c4d223a575f63904 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a013de7daa7bf9d8a5f59e292c2a01401568d738 Original-Change-Id: I8ddf9e65a8ac3d4b09032a741b725c78251f14c9 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243212 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9778 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 19:49:37 +0000