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2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie@google.com> Acked-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-04Don't unconditionally show ChromeOS optionsStefan Reinauer
Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/848 Reviewed-by: Martin Roth <martin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
From wikipedia: Intel Turbo Boost is a technology implemented by Intel in certain versions of their Nehalem- and Sandy Bridge-based CPUs, including Core i5 and Core i7 that enables the processor to run above its base operating frequency via dynamic control of the CPU's "clock rate". It is activated when the operating system requests the highest performance state of the processor. Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/844 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-03smbios: add support for onboard devices extended informationStefan Reinauer
Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/607 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02S3 code whitespaces changes.zbao
some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02Add sb800 spi support.zbao
It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02x86, oprom: ensure DF is always clearedMathias Krause
The Option ROM might mess with the EFLAGS register and break assumptions the C part of coreboot implicitly has, e.g. the state of the direction flag. Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS value after the Option ROMs has finished and always clear the direction flag before calling the C part of the interrupt handler. Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/837 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-02[ChromeOS] Don't initialize VGA Option ROM in normal modeStefan Reinauer
ChromeOS features two different modes: normal mode and developer mode (aka jailbreak mode). In developer mode, we need to display a warning screen for security reasons. However, in normal mode we want to boot blazingly fast. Therefore we don't run (VGA) option ROMs, unless we have to print something on the screen before the kernel is loaded. Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/829 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add EC component for SMSC MEC1308/1310Stefan Reinauer
Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/828 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add support for ITE IT8772F SuperI/O chipStefan Reinauer
Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add a helper function to determine the number of enabled CPUsStefan Reinauer
Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Align: Make sure 1 is treated as unsigned long instead of intStefan Reinauer
... and drop duplicate definition in via/epia-n code. Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/820 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add Google ChromeOS vendor supportStefan Reinauer
Google's ChromeOS can be booted super fast and safely using coreboot. This adds the ChromeOS specific code that is required by all ChromeBooks to do this. Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Fix issues with x86 memcpyMathias Krause
The x86 memcpy() implementation did not mention its implicit output registers ESI, EDI and ECX which might make this code miscompile when the compiler uses the value of EDI for the return value *after* the 'rep movsb' has completed. That would break the API of memcpy as this would return 'dst+len' instead of 'dst'. Fix this possible bug by removing the wrong comment and listing all output registers as such (using dummy stack variables that get optimized away). Also the leading 'cld' is superflous as the ABI mandates the direction flag to be cleared all the time when we're in C (see <http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites that might require it to be cleared explicitly (SMM might come to mind, but it clears the DF itself before passing control to the C part of the SMI handler). Last but not least fix the prototype to match the one from <string.h>. Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/836 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-31Whitespace fixesPatrick Georgi
Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/834 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
Use CPUID to get MAXPHYADDR and set MTRR masks correctly. Also only BSP CPU clears MTRRs and initializes its Local APIC. Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/686 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/604 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/644 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/454 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
Delete dead CAR code and whitespace fixes. Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/643 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/641 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/606 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Makefile: rename romstage linking filenamesKyösti Mälkki
$(obj)/location.txt -> $(obj)/romstage/base_xip.txt $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/812 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Makefile: split romstage linking to separate rulesKyösti Mälkki
After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/803 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Fix coreboot makefiles not to produce half baked output.Kyösti Mälkki
There were cases where output file was generated and modified within a recipe. If make was interrupted, it could exit with an output file that appears as up-to-date, but was generated with incomplete recipe. The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Drop obsolete TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/832 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-30use movsl for copying resume memory backStefan Reinauer
It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/755 Reviewed-by: Mathias Krause <minipli@googlemail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Don't unconditionally add support for cardbus and pci-x devicesStefan Reinauer
It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/756 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add DEBUG_TPM option to Debugging menuStefan Reinauer
instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Don't re-init EBDA in S3 resume path.Duncan Laurie
I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Prepare the BIOS data areas before device init.Duncan Laurie
Since we do not run option roms in normal mode nothing was initializing the BDA/EBDA and yet Linux depends very much on it having sane values here. For the most part the kernel tries to work around this not being initialized, but every once in awhile (1/300 boots or so) it would end up reading something that looked sane from BDA but was not and then it would panic. In this change the EBDA is unconditionally setup before devices are initialized. I'm not set on the location in dev_initialize() but there does not seem to be another place to hook it in so that it runs just once for ALL platforms regardless of whether they use option roms or not. (possibly hardwaremain?) The EBDA setup code has been moved into its own location in arch/x86/lib/ebda.c so it can be compiled in even if the option rom code is not. The low memory size is still set to 1MB which is enough to make linux happy without having to hook into each mainboard to get a more appropriate value. The setup_ebda() function takes inputs so it could be changed for a mainboard if needed. OLD/BROKEN would read garbage. Examples from different boots: ebda_addr=0x75e80 lowmem=0x1553400 ebda_addr=0x5e080 lowmem=0x3e51400 ebda_addr=0x7aa80 lowmem=0x2f8a800 NEW/FIXED now reads consistent values: ebda_addr=0xf6000 lowmem=0x100000 Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/769 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30vga_io.c is not needed unless CONFIG_VGA is setStefan Reinauer
hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add Kconfig options to enable TSEG and set a sizeDuncan Laurie
Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Make cpuid functions usable when compiled with PICDuncan Laurie
This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Also add a new CPUID extended function to query with ECX set. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/764 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Make PCI CONF2 support a compile time optionStefan Reinauer
It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/758 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add more timestamps in coreboot.Stefan Reinauer
This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/749 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Fix coreboot makefiles not to produce half baked output.Vadim Bendebury
It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-03-30Add timestamps for selfboot and acpi wakeDuncan Laurie
Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Make TPM driver work in rom stage.Stefan Reinauer
Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/738 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-30Add TPM support to corebootStefan Reinauer
and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add Google ChromeOS vendorcode directoryStefan Reinauer
... and hook it up in Kconfig. More code to come. Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add native memset() function on x86Stefan Reinauer
Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/737 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-30Add faster, architecture dependent memcpy()Stefan Reinauer
Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/736 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
The cbmem console structure and car global data are put in their own section, with the cbmem console coming after the global data. These areas are linked to be where CAR is available and at the very bottom of the stack. There is one shortcoming of this change: The section created by this change needs to be stripped out by the Makefile since leaving it in confuses cbfstool when it installs the stage in the image. I would like to make the tools link those symbols at the right location but leave allocation of that space out of the ELF. Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 03:28:43 +0000