summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2017-06-27nb/intel/sandybridge: Fill in acpi_namePatrick Rudolph
Fill in acpi_name to return proper ACPI names. To be used with SSDT generators. The ACPI names have to match those already used in ASL code. By providing the ACPI name it can be retrieved by the acpi_device_name() method and doesn't need to be hardcoded in SSDT generators any more. GFX0 is used in drivers/intel/gma/acpi/pch.asl. MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl. Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27mb/google: Remove ChromeEC builds for auron and rambiMartin Roth
The ChromeEC board directories for auron and rambi have been removed from the latest version of ChromeEC. Remove them here so the submodule can be brought forward. Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27mainboard/google/poppy: Update world facing camera sensorV Sowmya
Update the world facing camera sensor to OV13858 and also add delay of 5ms after xshutdown rising which indicates system ready status. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27mainboard/google/poppy: Add clock frequency for camera sensorsV Sowmya
Add clock frequency property into _DSD ACPI object and set it to 19.2MHz for camera sensors. Upstream camera kernel has added a check for clock frequency in sensor probe function and without this property sensor probe fails. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20294 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27lib/coreboot_tables: Zero framebuffer structureDuncan Laurie
Zero the framebuffer structure so if it is not filled in (either if no display is present or if there is an error) then it does not provide garbage data to the payload. This was noticed when booting a board without a display attached as the payload wrote to the framebuffer at a random address. With this change the payload can properly handle the case where a display is not attached and not corrupt memory. Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-26vendorcode/amd: Drop multiple copies of gcc-intrin.hStefan Reinauer
Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26vendorcode/amd: Unify gcc-intrin.hStefan Reinauer
Most of these functions go unused most of the time, but in order to not keep several copies around, let's make sure we are using the same file everywhere first. Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I91ababb3bf7aa1ab0f71bb005c4685e81bb4d92f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26amd/gardenia: Fix most checkpatch errorsMarshall Dawson
Correct all checkpatch errors but leave two errors in place that are caused by AMD typing. Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26amd/gardenia: Switch to soc/amd/stoneyridgeMarc Jones
Switch Garnenia mainboard to single soc/ directory structure. Change-Id: I095804d603bcccf324d3244965081a9dccba62ae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
As per latest BWG, ucode reloading should be done at the end of Mp Init, i.e., after PRMRR and other features are enabled. No reloading specifically after SMM Relocation is required. As, in the Common CPU MP Init code, we are already doing a uCode load at the end of MP Init Feature Programming, hence, the uCode loading after SMM relocation can be removed. Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar
This patch uses the common CPU Mp Init code. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-23soc/intel/common/block: Add common MP Init codeBarnali Sarkar
This patch contains State Machine callbacks init_cpus() and post_cpu_init(). Also, it has the SOC call for CPU feature programming. Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
It does not work to enable the LPC range in the function mainboard_init() because the LPC bus driver closes the range during PCI enumeration again. For this reason, enabling decoding of the address range for COM 3 will be done at a later point in time - mainboard_final(). Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-23siemens/mc_apl1: Disable XDCIMario Scheithauer
With enabled XDCI support we are not able to use USB port 0 over XHCI driver. For this reason, we disable XDCI into devicetree.cb. Change-Id: I1ed721d9ffd44a920a6f1f16855d5b7ceb1b17c5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-22cpu/allwinner/a10/clock.h: Add missing bracketElyes HAOUAS
Code checked manually Change-Id: I92f0b5d47c60c259171c4db90fb5003f4eb8580b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-22sb/amd/rs780/gfx.c: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I5a9596328c028d570303e9390c0133b19b97d683 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22cpu/x86: Use do while loopPaul Menzel
With the do while loop, it can be avoided do use an infinite loop with a break condition inside. Change-Id: I030f6782ad618b55112a2f0bac8dda08b497a9f1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/20269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-22device/dram/ddr3.h: Add brackets around macroArthur Heymans
This fixes improper dram frequency being displayed in sandy bridge native raminit. Change-Id: I1fe4e4331f45ce1c21113c039b8433252326293d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-22nb/intel/sandybridge/raminit: Fix dual DIMM command ratePatrick Rudolph
On boards that are able to take two DIMMs per channel the command rate should be 2T. It is possible to use 1T with load reduced "1T" DIMMs, but it's not clear how to detect those DIMMs. Raminit might fail for those who do not have such DIMMS installed. Hardcode command rate of 2T to make sure raminit works on dual DIMM per channel boards (currently only desktop boards). The command rate of 1T is still tested if only 1 DIMM per channel is present. Will decrease performance on quad slot mainboards, if two DIMMs are installed in one channel and previously 1T have been selected. Tested on ASRock B75 Pro3-M. Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-22nb/intel/haswell/raminit: Die if cbmem_add() failsNico Huber
Maybe we could go on, but cbmem_add() failing is a very bad sign. Should fix coverity CID 1376384 (Null pointer dereferences (NULL_RETURNS)). Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7 Found-by: Coverity Scan #1376384 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20280 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22arch/x86/smbios: Fix scope of variable declarationNico Huber
Fix up for 1b5eda0 (arch/x86/smbios: Fix undefined behavior) which introduced the variable `tmp` and used it out of scope. Should fix coverity CID 1376385 (Memory - illegal accesses (RETURN_LOCAL)). Change-Id: I8d4f664fc54faf6beb432b939dda4ddf93cf5d3e Found-by: Coverity Scan #1376385 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22soc/rdc: Remove r8610 SoCMartin Roth
Bifferboard was the only board that used this chip, and it has now been removed. Removing the chip as well. If there is desire to continue work on the board, it can be found in the 4.6 branch. Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-22mainboard/bifferos: remove bifferboardMartin Roth
This board can't be found to be tested, and compiles romstage with romcc. If desired, it can be continued in the 4.6 branch. Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-22drv/intel/gma/acpi: Fix copyright headerPatrick Rudolph
Use full text GPLv2 header. Change-Id: I937aed725ebf0d2e12c52ac4d94794830fbd764d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-22arch/x86: Make rdrand.c clang friendlyStefan Reinauer
rdrand64() is not clang friendly. Actually it looks like the function is incorrect on 32bit x86 for all compilers including gcc, but gcc won't care because the function is never called on x86: src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a' : "=a" (*rand), "=qm" (carry)); ^ 1 error generated. Guard the code correctly if ENV_X86_64 is not set. Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22cpu/x86/sipi_vector: use macros for CR0 flagsAaron Durbin
Use the existing macros for CR0 to set the flags in the SIPI vector code. Change-Id: Iad231b7611b613512fd000a7013175e91542ac10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-22cpu/x86/smm: use macros for CR0 flagsAaron Durbin
Use the existing macros for CR0 to set the flags in the SMM stub. Change-Id: I0f02fd6b0c14cee35ec33be2cac51057d18b82c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20242 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-22cpu/x86/smm: fix up types in module loaderAaron Durbin
For sizes and dimensions use size_t. For pointer casts use uintptr_t. Also, use the ALIGN_UP macro instead of open coding the operation. Change-Id: Id28968e60e51f46662c37249277454998afd5c0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20241 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-21cr50: process uninitialized values gracefullyVadim Bendebury
The vboot code tries reading rollback protection indices from the TPM, and if the attempt to read returns TPM_E_BADINDEX, it decides that the TPM has not yet been initialized for the Chromebook use, and needs to be taken through the factory initialization sequence. TPM_E_BADINDEX is an internal representation of the TPM error 0x28b, generated on attempts to read a non existing NVMEM space. If the space exists, but has never been written the TPM returns error 0x14a. This condition (the space exists but not written) could happen if the previous factory initialization attempt was interrupted right after the space was created. Let's map this error to the same internal representation (TPM_E_BADINDEX) so that the Chrome OS device could recover when this condition occurs. BRANCH=reef, gru BUG=b:37443842 TEST=verified that the Pyro device stuck in TPM error state recovered when this patch was applied. Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/20299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20soc/intel/common: Add SMM common code for Intel PlatformsBrandon Breitenstein
SMI code is very similar across Intel platforms. Move this code to common/block/smi to allow it to be shared between platforms instead of duplicating the code for each platform. smihandler.h has already been made common so all it will contain is name changes and a move to the common block location. Due to moving smihandler code, APL changes are bundled here to show this change. Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/19392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20soc/intel/quark: Add legacy SPI flash controller driverLee Leahy
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-20mb/google/poppy: Add camera devices power sequencing through ACPI power ↵V Sowmya
resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20mb/google/poppy: Configure ports and endpoints for sensor and CIO2 devicesV Sowmya
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20google/fizz: Enable onboard lanShelley Chen
Enable RT8168_GET_MAC_FROM_VPD in fizz Kconfig. BUG=b:62090148, b:35775024 BRANCH=None TEST=Boot to kernel. Insert mac address into VPD vpd -s ethernet_mac=<address> reboot the system. Ensure we have ip address and corresponding mac address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: I00f63dcb56a2c9a4600c8461bc94e06ec5ab2d81 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20drivers/net/r8168: Get mac address from VPDShelley Chen
If RT8168_GET_MAC_FROM_VPD selected, use r8168 driver with some slight mods to check the VPD for a mac address. Otherwise, check for mac address in cbfs. Use default mac address if cannot find one. BUG=b:62090148, b:35775024 BRANCH=None TEST=Boot to kernel. Insert mac address into VPD vpd -s ethernet_mac=<address> reboot the system. Ensure we have ip address and corresponding mac address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20google/fizz: Enable cr50 over SPIShelley Chen
By default disabled. Will need to add FIZZ_USE_SPI_TPM config to enable. BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure that TPM works in verstage CQ-DEPEND=CL:530184 Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20134 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-20google/fizz: Enable cr50 over i2cShelley Chen
BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure verstage doesn't have any TPM errors CQ-DEPEND=CL:530185 Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-20arch/x86/smbios: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that's not aligned to the size of access is undefined behavior. The report triggered for smbios_cpu_vendor(). Also fixes the same issue in smbios_processor_name() found by inspection. Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-20arch/x86/ebda: Change memcpy() to endian wrappersRyan Salsamendi
Change memcpy()s and memset()s to endian.h wrappers for consistency and safety. Add zero_n() wrapper to safely clear memory. Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20commonlib/storage: Fix MMC buildLee Leahy
Add missing includes to build mmc.c. TEST=Build and run on Galileo Gen2 Change-Id: I0dea597272e5ece97843704a159aa546a8d77ff0 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-19mb/google/poppy: Add MIPI camera support.V Sowmya
This patch adds mipi_camera.asl, * Add TPS68470 PMIC related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mainboard/google/{poppy,soraka}: Remove MIPI camera support from devicetree.cbV Sowmya
Remove MIPI camera related register entries from devicetree.cb. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy and soraka. Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19nb/intel/pineview/raminit: Remove very long delaysArthur Heymans
These delays, adding up to 600 ms, don’t seem to be needed, so remove them. TESTED on d510mo, boots fine without. Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Damien Zammit <damien@zamaudio.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 04:32:13 +0000