summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-10-09northbridge/amd/amdk8: Remove commented codeElyes HAOUAS
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16893 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/lx: Remove commented codeElyes HAOUAS
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/pi/00730F01: Remove commented codeElyes HAOUAS
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16890 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdmct/mct_ddr3: Remove commented codeElyes HAOUAS
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16889 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family16kb: Remove commented codeElyes HAOUAS
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16888 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15rl: Remove commented codeElyes HAOUAS
Change-Id: I5f45a4cd5661140f57aa37e86cc8a34622da3de5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family10: Remove commented codeElyes HAOUAS
Change-Id: I7966f996a4291cc6b97b53aba59b43358de94e45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16886 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdfam10: Remove commented codeElyes HAOUAS
Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabledYork Yang
When timestamp is enabled, the system hangs because the timestamp data is not yet available. Add a temporary work around that starts the timestamp after the FspInit() making this data available. Verified on Intel Camelback Mountain CRB and ensured that system can boot to payload with timpstamp feature enabled. Change-Id: I59c4bb83ae7e166cceca34988d5a392e5a831afa Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/16894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09soc/intel/fsp_broadwell_de: Remove the enforced fsp1.0 APIs call sequenceYork Yang
The enforced FSP 1.0 APIs call was used to work around an fsp1.0 driver issue. As the issue has been addressed in fsp1.0 driver (Change 9780), remove the enforced workaround. Otherwise will see error message 'FSP API NotifyPhase failed' in serial log. Verified on Intel Camelback Mountain CRB and confirmed that the serial log error message regarding the 'FSP API NotifyPhase failed' is gone. Change-Id: Iafa1d22e2476769fd841a3ebaa1ab4f9713c6c39 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/16892 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09drivers/intel/wifi: Add depends on ARCH_X86Martin Roth
When compiling a non-x86 platform with DRIVERS_INTEL_WIFI enabled, we get the build error: src/drivers/intel/wifi/wifi.c:17:30: fatal error: arch/acpi_device.h: No such file or directory acpi_device.h only exists in the x86 architecture directory. Change-Id: Id0e29558336bf44e638cfcb97c22f31683ea4ec7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16906 Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-10-08google/oak: Increase the driving strength for 4GB DRAMsPH Hsu
Some PVT units encountered DRAM calibration failure during power on/off tests. The failure is caused by higher impedance of the DRAM on those units. So increase the driving strength for 4GB DRAMs. BUG=chrome-os-partner:57392 TEST=run cold reboot 100 times on PVT units which have DRAM calibration issue. Change-Id: I8a329093db3f1def566e4b7afec3c4f4bfe44c6a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf1aa5ade856af433fa056f51a20d18553ae241d Original-Change-Id: I0d1776cd1a5892d1f82e9bf414620d1ef6d29132 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/394451 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-08google/gru: Add USB 2.0 PHY tuning for Kevin PHY0 and PHY1William wu
We found that Kevin board PHY0 and PHY1 eye-diagram margin is not enough to make compliance test pass, and the PHY0 USB SI is worse than PHY1, because of the higher PCB impedance. For PHY0, we can't improve the eye-diagram by SW PHY tuning, so we need to reduce the RBIAS resistance from 133 ohm to 115 ohm, it can help to increase the eye-height. For PHY1, we can improve the eye-diagram by setting the max pre-emphasis level. And after the above change, the USB2 signal amplitude will become larger at the test point near to SOC USB2 PHY, in order to avoid mis-trigger the disconnect detection (650mV), we need to disable pre-emphasize in eop state. BRANCH=None BUG=chrome-os-partner:53863 TEST=do USB 2.0 compliance test for Kevin C0 and C1 port. Change-Id: I95c0acd79623aeca9a0ae077b1dd3836d91fe561 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de3cdef128966d76e7d8e2ebd641763b911c3ad5 Original-Change-Id: I00cb325b9938e4276cc77b5d6f5faa7023379608 Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/390615 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16911 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-08rockchip/rk3399: Add Type-C PHY initWilliam wu
Though we don't use Type-C PHY to support USB3 in firmware, we still need to initialize the Type-C PHY, and make sure the power state of pipe is always fixed to U2/P2. After this, we can force USB3 controller to work in USB2 only mode. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot from USB. Change-Id: I95bb96ff27d4fecafb7b2b9e9dc2839b5c132654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ec98507845276119d8a9d5626934dedcb35f2dd Original-Change-Id: Ie3654cd1c1cb76b62aa9b247879b60cbecee0155 Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/391412 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16910 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07soc/intel/apollolake: Disable HECI2 device reset on S3 resumeAndrey Petrov
Converged Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07vendorcode/intel/fsp: Update UPD headers for FSP 157_10Brandon Breitenstein
These header files contain a few new UPDs. The EnableS3Heci2 UPD will be used to save ~100ms from the S3 resume time on Apollolake chrome platforms. BUG=chrome-os-partner:58121 BRANCH=none TEST=built coreboot for reef and verified no regressions Change-Id: I1f324d00237c7150697800258a2f7b7eed856417 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/reef/variants/pyro: Add support for GPIO output polarityMartin Roth
commit 028200f7 - x86/acpi_device: Add support for GPIO output polarity updated ACPI_GPIO_OUTPUT to ACPI_GPIO_OUTPUT_ACTIVE_HIGH for the other boards that needed it, but pyro wasn't in the tree when it was initially pushed. Now that pyro is in the tree, it needs to be updated as well. Change-Id: I617999b06ee584e0543d7ae3232bb2be2ff7429c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16930 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-10-07soc/intel/apollolake: Implement stage cache to improve resume timeBrandon Breitenstein
This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16833 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07src/southbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/arch: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Ia2fc3d5ea88d61ba7c4a1daebfe74a24948c8f6e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/cpu: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I0903b7ca9eada4beacfcdbcacddec23c3515651e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/southbridge: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Ic3b599d49a4c03ad8035c558b975f31cb91d253b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16862 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07cpu/amd/geode_gx2: Remove unnecessary semicolonElyes HAOUAS
Change-Id: I5585eac9fec5180254c7d3cc966441e9794e8390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16858 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/drivers: Remove whitespace after memcpy & memsetElyes HAOUAS
Change-Id: If79eb706b6d44f7c34dfe31a1545f5850870b334 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16866 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/mainboard: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Ie2a047d35e69182812c349daedc5b3b5fde20122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16860 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/mainboard: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I35cb7e08d5233aa5a3dbb4631ab2ee4dc9596f98 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07x86/acpi_device: Add support for GPIO output polarityFurquan Shaikh
Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-07x86/acpi_device: Fix writing of array propertyFurquan Shaikh
Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. This DP_TYPE_TABLE does not have a value which is written. Thus, acpi_dp_write_array needs to start counting from the next element type in the array. Fix this by updating the initialization in for loop for writing array elements. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that the correct number of elements are passed for add_gpio in maxim sdmode-gpio. Change-Id: I8e1e540d66086971de2edf0bb83494d3b1dbd176 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-07ec/google/chromeec: Add minimum delay between SPI CS assertionsJulius Werner
Some Chrome OS ECs require a small amount of time after a SPI transaction to reset their controllers before they can service the next CS assertion. The kernel and depthcharge have always enforced a 200us minimum delay for this... coreboot should've done the same. BRANCH=gru BUG=chrome-os-partner:58046 TEST=Booted Kevin in recovery mode, confirmed that recovery events got logged with correct timestamps in eventlog. Change-Id: I32ec343f3293ac93729d3e6e2f43d7605a396cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9e4696533d4318ae7c8715b71ab963d8897c16c Original-Change-Id: I6a7baf7859d5d50e299495d118e7890dcaa2c1b0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/392206 Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/16885 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: drive WLAN_MODULE_RST# low as early as possibleBrian Norris
GPIO1_B3 (WLAN_MODULE_RST#) defaults as a pull-up input, but it is also "pulled up" by 1.8V_WLAN. However, 1.8V_WLAN remains low for some time during early boot. This leaves the signal floating somewhere in the middle. This has two potential issues: (1) we're leaking some power for some (hopefully) short period of time (2) we are possibly screwing with the Wifi power sequence; we aren't supposed to deassert PDn (i.e., MODULE_RST#) until all the rails have fully ramped for some period of time Neither of the above issues are likely to be significant, but it is nice to fix, I expect. BRANCH=gru BUG=chrome-os-partner:54026 TEST=measure WLAN_MODULE_RST# on scope at boot time Change-Id: Ia6af9ad6954ad8feeda33015e3f205842380939e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e890a2787bf034d3358a33fc88c2dd8078593ab Original-Change-Id: I120e26ad0ca486a326874986e142dcaee965b62d Original-Signed-off-by: Brian Norris <briannorris@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/388009 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16882 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07Revert "soc/intel/apollolake: Add pmc_ipc device support"Furquan Shaikh
This reverts commit 28821dbb2261267462a7e9b0cc1c23b51af2d3ee. (https://review.coreboot.org/16649) This change causes the kernel to boot really slow. Maybe there is an interrupt storm that prevents the kernel from making any progress. Reverting until the proper kernel dependency is met. BUG=chrome-os-partner:57364 BRANCH=None TEST=Kernels boots to prompt fine on DVT. Change-Id: I1c9913b4476a08303f9dd887b8631601c847dcf7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7014ee1bb88df7a2d7f6b3dced797fef75b252d Original-Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1 Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/391233 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/16881 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07soc/qualcomm/ipq40xx: Fix GPIO pull up config.Kan Yan
BUG=b:31690391 TEST=Tested with board ID BRANCH=none Change-Id: I9a2b7eec111a79827f72a506942a8ec833ba7e60 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f23e2b6e72491aaafa15774f9bded3e14363abbc Original-Change-Id: I23183db29d7f7dd812e94ab6a1f2f1329c46ac60 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388778 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/16770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: Actually remove big CPU initialization from bootblockJulius Werner
CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h@gmx.de> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16769 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: select rank before triggering trainingDerek Basehore
This selects the rank to train before training is triggered. This is to prevent any race conditions with the hardware. BRANCH=none BUG=chrome-os-partner:56940 TEST=stressapptest -M 1536 -s 1000 Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/387907 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: 云平 汤 <typ@rock-chips.com> Reviewed-on: https://review.coreboot.org/16768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07Gale: Fix the orange color to match the UX docSuresh Rajashekara
UX Doc = go/gale-hw-ui This color wasn't changed earlier as the change wasn't done in the OS also. However, since we cannot change this later in FW (but OS can change anytime), I am making this change after discussing with the UX team. BUG=b:31501528, b:31633562 TEST=Change the device state to 'recovery mode' to observe the new color. BRANCH=none Change-Id: Ia91f14eb77492095cb41a9de0bb9790e72aa4851 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36a3d8c6eabbc0b23d0a15d5bddc5ed3bdeebe70 Original-Change-Id: I88768b94cf91804a6005e44b1a168e059698ec4b Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388206 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Christopher Book <cbook@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/16767 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: Improve dram stability when run at high frequencyLin Huang
There are two modifications in the driver: 1. Correctly set speeds based on DDR frequency. Control the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. Configure the number of cycles for the phy clock pll wait time after locking, based on the DDR config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16722 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-07RISCV: update the encoding.h file.Ronald G. Minnich
Change-Id: I8997e927d82363921a3ff17580b9a575acc1ce16 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/16919 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-07google/gru: set W2W_DIFFCS_DLY to 5Lin Huang
PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time and there should be more cycles to switch the delay line, so update the W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: pass apio number to arm-trust-firmwareLin Huang
To save power when entering suspend, gpios 2 to 4 need to be set to input and 'pull none' mode. Pass the APIO configuration to ATF so it can do a proper job here. BRANCH=None BUG=chrome-os-partner:56423 TEST=run suspend_stress_test on kevin board Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/378475 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: pass the gpio power supply enable pin to bl31Lin Huang
We need to disable some regulators when the device goes into suspend. This means that we need to pass some gpios to bl31, and disable these gpios when bl31 runs the suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07mainboard/google/reef: add pyro variant.Kevin Chiu
Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-06i2c/ww_ring: LED changes as per UX team feedback.Suresh Rajashekara
Colors and patterns as defined by the UX team BUG=b:31501528 TEST=Move the device to different states in FW using rec and dev button and verify the colors BRANCH=None Change-Id: I66d41a54590cd3ce4e5202c7cfa890f462fe195e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 703559d5dddaeeb7d435d6cadbb2009a1b7a76c8 Original-Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7 Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387258 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Christopher Book <cbook@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/16718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: Configure USB3 controller to work in USB2 only modeLiangfeng Wu
In USB2 only mode, the Type-C PHY will be held in reset and only the USB2 logic of the USB3 OTG controller and PHY will be used over the USB2 pins on the Type-C connector to support Low, Full and High-speed USB operation. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot from USB. Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93 Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/385837 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16717 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: rk3399: improve write leveling flowJianqun Xu
To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow to get the proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16716 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06google/gru: Shrink RW_ELOG region to 4KBJulius Werner
Since there's currently a limitation in coreboot's code that prevents more than 4KB to be used by the eventlog anyway, this patch shrinks the available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove prudent later if we ever resolve that limitation, so that tools can rely on the area in the FMAP being the same as the area actually used by the read-only firmware code on these boards. BRANCH=gru BUG=chrome-os-partner:55593 TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a reboot loop to exhaust eventlog space, confirmed that the shrink code kicks in as expected before reaching 4KB. Change-Id: I3c55d836c72486665a19783fe98ce9e0df174b6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 05efb82ca00703fd92d925ebf717738e37295c18 Original-Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384585 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: Move TTB to the end of SRAMJulius Werner
We found that we may want to load some components of BL31 on the RK3399 into SRAM. As usual, these components may not overlap any coreboot regions still in use at that time, as is already statically checked by the check-ramstage-overlaps rule in Makefile.inc. On RK3399, the only such regions are TTB and STACK. This patch moves the TTB region back to the end of SRAM (right before STACK), so that a large contiguous region of SRAM before that remains usable for BL31. BRANCH=gru BUG=None TEST=Booted Kevin. Change-Id: I1689d0280d79bad805fea5fc3759c2ae3ba24915 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d4c6c6f6cc0efe97d6962a81e309a1c040d1def Original-Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384635 Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16714 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: rk3399: improve sdram noc timingLin Huang
sdram noc timing will affect ddr latency, this patch improves rk3399 sdram noc timing so improve memory performance. BRANCH=gru BUG=chrome-os-partner:57248 TEST=Boot from kevin board Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642 Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382725 Original-Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Sonny Rao <sonnyrao@chromium.org> Original-Commit-Queue: Sonny Rao <sonnyrao@chromium.org> Reviewed-on: https://review.coreboot.org/16713 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: spi: Add support for 16-bit APB readsSimon Glass
With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck. Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash. In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes. The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB. CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be. Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ec250b4931c7d99cc014e32ab597fca948299d08 Original-Change-Id: Idc5b7e5d82cdbdc1e8fe8b2d6da819edf2d5570c Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381312 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: lower kevin board sdram frequency to 800MHzLin Huang
We found some boards are not stable when sdram is run at 933Mhz. Before we can fix it, we need to lower the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260 and extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06arm64: Use 'payload' format for ATF instead of 'stage'Simon Glass
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg@google.com> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 12:34:06 +0000