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2007-10-24smaller changes to silence build warnings. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24analog changes for the cpu_driver structures...Stefan Reinauer
make them const before putting them into the read-only segment... (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24Ever wondered where those "setting incorrect section attributes forStefan Reinauer
rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23fix a whole bunch of warnings. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23drop unused variable (and thus warning). trivial patch.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23Add support for the Intel mFCPGA 478 socket. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23The s2882 ships with a 1MB rom chip. The targets/tyan/s2882/Config.lb fileWard Vandewege
assumes a 1MB rom chip. Hence the default position for the VGA bios should also assume a 1MB rom chip, not a 512KB chip. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Fix typo (trivial)Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Add support for a precompressed LZMA payload (trivial).Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22This patch adds support for K8T890CE northbridge.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Trivial: remove unused variable.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22This is a hack for easier testing of GRUB2 in LinuxBIOSv2Stefan Reinauer
since it is still our most wide-spread codebase. The patch is pretty trivial, and nobody except Torsten even looked at it in a week, so.... Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-21Put the print in the right place. This is trivial patch but a veryRonald G. Minnich
serious issue, so I am self-acking. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-21I am signing off and acking this trivial patch, as I just wasted severalRonald G. Minnich
days on a function named pll_reset that, on exit, says "Done cpuRegInit", and which, in turn, made me think it was a lot farther along that it was. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17Add a debug message to keyboard init. This helped isolate at least oneCarl-Daniel Hailfinger
case of keyboard failure (the keyboard initialization was never hit). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17Fix up totally broken Super I/O setup on the MSI MS-7260 (K9N Neo).Uwe Hermann
This has not been working at all until now. With this fix, keyboard, mouse, parallel port, and the Super I/O sensors work fine (tested on actual hardware). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Add resource size and resource granularity reporting to device_util.c.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Completely rip out / replace the ASUS P2B code (which wasn't really working),Uwe Hermann
replacing it with a minimal, but working, framework which will be expanded. Drop a bunch of useless and duplicated files, add missing license headers. I'm self-acking it this time, the diff is a huge unreadable mess and the old code is broken anyway... This code is tested to build fine, and can boot a Linux kernel up to a login-prompt via FILO (IDE). This is verified on actual hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA)Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-14Fix the resource end in amdk8/northbridge.c.Rudolf Marek
Without this bugfix, the resource for the PCI/ISA video memory at 0xa0000 - 0xbffff is too big, i.e. it goes up to 0xcffff instead of just 0xbffff as it should. Here's the diff from two runs of the tool from http://www.linuxbios.org/pipermail/linuxbios/2007-June/022449.html on the MSI MS-7260 (K9N Neo), with and without the bugfix. After applying, the resource size is correct again. --- dumpres_lb_pci_vgacard_without_resfix.txt +++ dumpres_lb_pci_vgacard_with_resfix.txt @@ -11,7 +11,7 @@ MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 -MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W Dstnode:0 DstLink 0 +MMIO map: #5 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0 MMIO map: #6 0x00fc000000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0 MMIO map: #7 0x00fd200000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0 MMIO map: #0 0x000000 - 0x003fff Access: R/W ISA VGA Dstnode:0 DstLink 0 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-11Set the default video memory to 0 MB for all GX1 boards which don't yetUwe Hermann
use that feature in order to not waste RAM. Also, add missing CONFIG_VIDEO_MB for the eaglelion/5bcm, which should fix the build for that board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10This patch adds the CONFIG_VIDEO_MB option to boards thatCorey Osgood
currently don't have it but need it to compile with the new Geode GX1 VGA support. This sets the size at 4MB, which was the size previously defined in the VGA code. Signed-off-by: Corey Osgood <corey.osgod@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-09Minor cosmetic changes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-09Add support for the BCOM WinNET100 (used in the IGEL-316 thin client).Juergen Beisert
See http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial for hardware description and build tutorials. Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07Make the reserved video memory on Geode GX1 based systems configurable.Juergen Beisert
This makes sense on systems with small memories when the VGA feature is not used (CONFIG_VIDEO_MB = 0 in this case). On Geode GX1 based systems the following amount of memory should be reserved when VGA support is enabled: - 1MiB for VGA and SVGA resolutions - 2MiB for XGA resolution - 4MiB for SXGA resolution Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07Add missing '\n' to a printk_debug() and some other small fixesUwe Hermann
while I'm at it (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07Fix some issues with spaces in the code and Doxygen style documentation.Juergen Beisert
Painting the splash graphic is now ifdef'ed. Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05This patch will add support for the Geode GX1/CS5530 VGA feature. It's ableJuergen Beisert
to set up one of five screen resolutions (sorry no autodetection at runtime, resolution is selected at buildtime) and displays a graphic in the right bottom corner (splash screen). Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-01Thee lines in i82801xx_pci.c need to be removed. They cause theJoseph Smith
i82801DB to reset. See this thread for more info: http://article.gmane.org/gmane.linux.bios/26791 Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26Don't arbitrarily enable PERR# and SERR# for PCI devices. Marc Jones
It is platform specific. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-25As per suggestion from Yinghai Lu <yinghailu@gmail.com> this patchUwe Hermann
fixes the problems with PCI add-on cards not being detected or initialized on MCP55-based systems (PCI bridge decoding change). I have tested this on the MSI MS-7260 (K9N Neo) with a PCI VGA card, which worked fine in any of the three PCI slots. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24Various cosmetic changes and coding style fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22Fix another, similar typo as in r2800 (trivial).Uwe Hermann
Reported by Robert Millan. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22Fix typo which causes build error if CK804_USE_NIC is set (trivial).Uwe Hermann
This is tested with abuild so shouldn't break anything. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22Add SiS device IDs for further update.Morgan Tsai
Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21Fix abuild for the MSI MS-7260 (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21Add support for the MSI MS-7260 (K9N Neo) mainboard.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20The s2891 ships with a 1MB rom chip. The targets/tyan/s2891/Config.lb file ↵Ward Vandewege
assumes a 1MB rom chip. Hence the default position for the VGA bios should also assume a 1MB rom chip, instead of a 512KB chip. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19Add support for a precompressed LZMA payload (trivial).Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19Sorry, I mixed up two patches. Reverting this change.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19Add support for a precompressed LZMA payload (trivial).Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.Yinghai Lu
For example: in C51/MCP55 or C51/MCP51 Will allow 1. C51 at 0x10 to 0x14, and MCP at 0 to 4 2. C51 at 1 to 4, and MCP at 7 to 0x0a The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it needed), and will prevent us from putting them on bus 0. Typical values for c51/mcp55 or c51/mcp51: HT_CHAIN_UNITID_BASE = 0x10 # for C51 HT_CHAIN_END_UNITID_BASE = 0 # for mcp If only have mcp with c51, HT_CHAIN_UNITID_BASE = 0 # for MCP #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20 Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14This is a full rewrite of all the CS5530/CS5530A code. The previous code wasUwe Hermann
mostly undocumented, had a broken coding style, contained lots of dead code and had several other problems, e.g. it enabled write access to the ROM (why?), it unconditionally enabled primary/secondary IDE (which should have a config option) and that even _twice_ (which is um... wrong). The new code - has 'ide0_enable' and 'ide1_enable' config options (which actually work) to enable/disable the primary/secondary IDE interface in Config.lb. - Does _not_ enable write access to the ROM (or is there some good reason to do that? If so, it should at least have a config option). - Contains a bit more documentation. - Uses readable (and documented) #defines instead of hardcoded magic values. - aaand... it actually compiles ;-) Yep, that's right. The previous code wouldn't even build, as it hadn't been fully ported from v1 (still used v1 functions which are simply not available in v2). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13I still don't understand a word, but I tried to improve the documentation. ↵Stefan Reinauer
(trivial) Please fix this if you can. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13Fix abuild run of the MSI MS-6178 (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13Add a common/global failover.c file which can be used by allUwe Hermann
(or at least most) mainboards. This should put and end to copy-paste'ing the same file again and again for every mainboard. Fix the build for the MSI MS-6178 target (wrong location of the common failover.c file). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-12Add initial support for the Intel 810 based board MSI MS-6178.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Partial changes and fixup.Ronald G. Minnich
Removed reset.c and added copyright headers. Remove debug.c. It is not used and should not be here. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08Welcome to PC Engines and the ALIX 1C!Ronald G. Minnich
This is a geode LX board. There are timing settings that are not right yet, we are still trying to get our board to boot Linux :-) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Athlon64 x2 5000+ CPU.Torsten Duwe
A trivial one-liner for the CPU I happen to have. The sales docs said it's a "G1 revision", but the Rev F code works just fine. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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