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2020-06-06mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by halvor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: H9HKNNNCRMBVAR-NEH Byte# Current New Explanation 4 0x16 0x15 As per datasheet, density is 8Gb per logical channel. So value should be 0x15. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels 2 dies. Hence, 0x94 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x0460. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G64D4SQ-046 WT:A Byte# Current New Explanation 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels, 2 dies. Hence, 0x94. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by malefor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/ripto: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by ripto and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/jasperlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with JSL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. Change-Id: Ic52506b809c66b9f7cf25a100a959d85c67addf2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41876 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with TGL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. BUG=b:147321551,b:155239397 Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/board_info.c: Clean upElyes HAOUAS
Remove unused includes Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06arch/x86: Declare permanent_smi_handler()Kyösti Mälkki
Advertising SMI triggers in FADT is only valid if we exit with SMI installed. There has been some experiments to delay SMM installation to OS, yet there are new platforms that allow some configuration access only to be done inside SMM. Splitting static HAVE_SMI_HANDLER variable helps to manage cases where SMM might be both installed and cleared prior to entering payload. Change-Id: Iad92c4a180524e15199633693446a087787ad3a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06soc,southbridge/intel: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/emulation/qemu-q35: Control SMI related FADT entriesKyösti Mälkki
If running on older (like before 2.4.0) version of QEMU there is no SMI support, so never advertise SMI in FADT for the emulation. Behaviour if ACPI daemon tries to raise SMI under these conditions is unknown. Change-Id: I170058793798648c6713de1530d89ec2ac53e39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06mb/lenovo/t400,x200: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Ia61e50fb49719e9e18e81a27f355cdbd755a3f40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/roda/rk9: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/prodrive/hermes: Add new mainboard portChristian Walter
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-06soc/intel/xeon_sp/cpx: set up cpusJonathan Zhang
Set up cpus: * setup apic IDs. * setup MSR to enable fast string, speed step, etc. * Enable turbo Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-05google/trogdor: Remove RO_FSG regionJulius Werner
We decided to store the FSG on eMMC instead of SPI flash, so we don't need this region anymore. Getting rid of it allows us to put more space into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining amount to keep the FMAP alignment reasonable. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-06-05soc/amd/common/spi: add and use define for last FIFO positionFelix Held
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but turned out to be correct. Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-05soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devicesFurquan Shaikh
This change adds a helper function set_mmio_dev_ops() in chip.c which is used for setting the dev->ops for MMIO devices based on the comparison of MMIO address in device tree to the pre-defined base addresses in iomap.h. Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of i2c_acpi_name is restricted to i2c.c since it is not required to be exposed out of that file. Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-05sb/intel/bd82x6x: Remove dead codeAngel Pons
Drop functions that are not being used. Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-04Revert "mb/google/zork: Increase RO section to 5MB"Raul E Rangel
This reverts commit fddd101904188193197be10c8eae04e76386299b. Reason for revert: With FSP compression and non serial FSP we now have enough space in RO. Original change's description: > mb/google/zork: Increase RO section to 5MB > > The current size is too small to fit all the depthcharge assets. > Increasing it to 5MB gives us 648k of free space. > > $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT > FMAP REGION: COREBOOT > Name Offset Type Size Comp > cbfs master header 0x0 cbfs header 32 none > fallback/romstage 0x80 stage 524316 none > fallback/ramstage 0x80100 stage 96592 none > config 0x97ac0 raw 843 none > revision 0x97e80 raw 680 none > spd.bin 0x98180 spd 8192 none > etc/sdcard0 0x9a1c0 raw 8 none > locales 0x9a200 raw 141 LZMA (166 decompressed) > (empty) 0x9a300 null 3224 none > fspm.bin 0x9afc0 fsp 720896 none > (empty) 0x14b000 null 3992 none > fsps.bin 0x14bfc0 fsp 327680 none > pci1002,15d8,c1.rom 0x19c000 optionrom 54272 none > pci1002,15d8,c4.rom 0x1a9480 optionrom 54272 none > fallback/dsdt.aml 0x1b6900 raw 12727 none > locale_hi.bin 0x1b9b00 raw 10441 LZMA (239928 decompressed) > ... > locale_ko.bin 0x254f80 raw 11282 LZMA (231168 decompressed) > fallback/payload 0x257c00 simple elf 95169 none > (empty) 0x26f000 null 245656 none > apu/amdfw 0x2aafc0 raw 1277440 none > (empty) 0x3e2e00 null 688472 none > bootblock 0x48af80 bootblock 64 none > > BUG=b:130028876 > BRANCH=none > TEST=Built image with depthcharge and booted. > > Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1 > Signed-off-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850 > Reviewed-by: Martin Roth <martinroth@google.com> BUG=b:130028876, b:150746858 BRANCH=none TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle localhost ~ # flashrom -p host -r /tmp/main.bin flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) Calibrating delay loop... OK. coreboot table found at 0xcbe54000. Reading flash... SUCCESS localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3 area: 22 area_offset: 0x00c00000 area_size: 0x00400000 (4194304) area_name: WP_RO localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. SUCCESS localhost ~ # flashrom -p host --wp-status flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. WP: status: 0x0094 WP: status.srp0: 1 WP: status.srp1: 0 WP: write protect is enabled. WP: write protect range: start=0x00c00000, len=0x00400000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-04drivers/uart/acpi: Add new device driver for UART attached devicesDuncan Laurie
This driver generates an ACPI device object for a UART attached device with all of the expected device support handlers like different interrupt sources and power control GPIOs. Example use: chip drivers/uart/acpi register "name" = ""UDEV"" register "desc" = ""UART Attached Device"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" register "uart" = "ACPI_UART_RAW_DEVICE(115200, 64)" device generic 0 on end end Resulting in this ACPI device: Device (UDEV) { Name (_HID, "PRP0001") Name (_UID, Zero) Name (_DDN, "UART Attached Device") Method (_STA, 0, NotSerialized) { Return (0x0F) } Name (_CRS, ResourceTemplate () { UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.PCI0.UAR2", 0x00, ResourceConsumer, , Exclusive) GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer) { 0x0114 } }) Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) { Package (0x02) { "compatible", "google,cros-ec-uart" } } }) } Change-Id: Idfd2d9d2ab6990a82ddd401734c0d9b1b0b8f82d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-04acpi: Add support for writing UART device descriptorsDuncan Laurie
This change adds support for generating the device descriptor that corresponds to the UARTSerialBusV2() ACPI macro. The resulting ACPI code for ACPI_UART_RAW_DEVICE(115200, 64) is: UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.PCI0.UAR2", 0x00, ResourceConsumer, , Exclusive) Change-Id: I671ce2a499d74717d8677528c46ab3fbc1d7faf5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-04acpi: Accomodate non-standard UUIDs in device propertiesDuncan Laurie
There have been changes to the way device properties are supported in Linux[1] and Windows[2] which add flexibilty: - non-standard UUIDs can be used instead of only ACPI_DP_UUID - support for multiple different packages within the _DSD that associate different properties with unique UUIDs. To handle this I extracted the part that does the write of UUID and properties to a separate function and defined a new PACKAGE type which has the custom UUID as a name and can be used the same way that child properties are today. For example a PCIe root port for a USB4 port has a standard property indicating the USB4 reference, and then two custom properties which are defined for different attributes. Example code: /* Create property table */ acpi_dp *dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_reference(dsd, "usb4-port", usb4_path); /* Add package for hotplug */ acpi_dp *pkg = acpi_dp_new_table("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"); acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); acpi_dp_add_package(dsd, pkg); /* Add package for external port info */ pkg = acpi_dp_new_table("efcc06cc-73ac-4bc3-bff0-76143807c389"); acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); acpi_dp_add_package(dsd, pkg); /* Write all properties */ acpi_dp_write(dsd); Resulting ACPI: Scope (\_SB.PCI0.TRP0) { Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package () { "usb4-port", \_SB.PCI0.TDM0.RHUB.PRTA } }, ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package () { Package () { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package () { Package () { "ExternalFacingPort", One }, } }) } [1] https://patchwork.kernel.org/patch/10599675/ [2] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-04mb/google/volteer: Create voxel variantDavid Wu
Create the voxel variant of the volteer reference board BUG=b:157879197 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOXEL Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8ba5412be211730db84675927c500238cb20ff3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-04cpu/intel/slot_1: Select 16KiB bootblock if console is enabledKeith Hui
We previously confirmed [1] that bootblock will grow beyond current 8KiB size if console is enabled. Automatically change to 16KiB if user enabled it in menuconfig. [1] https://review.coreboot.org/c/coreboot/+/36775 Change-Id: Ic9988c77cf9677167a382aa4dc7dcfa2bc4cbe02 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41460 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-04mb/google/zork: create new variant for VilbozPeichao Wang
BUG=b:157499341 BRANCH=NONE TEST=FW_NAME="vilboz" emerge-zork coreboot Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41801 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-04soc/amd/picasso/Makefile: Allow absolute path for picasso firmwareRaul E Rangel
If AMD_PUBKEY_FILE contains an absolute path the resulting path is incorrect since it contains $(top). BUG=b:147042464 TEST=Build trembyle with absolute and relative path. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-04soc/intel/xeon_sp/cpx: add chip operation and PCIe enumerationJonathan Zhang
Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-04soc/amd/picasso: fix iomap for ACPI_PMKangheui Won
offsets for ACPI_PM are incorrectly configured for picasso SoC. Especially incorrect ACPI_PM_TMR_BLK makes kernel to spend 10 sec for trying to testing it on wrong address. Fix them to correct offset with hack for GPE0_BLK. BUG=b:147044624 TEST=build and boot on trembyle; PM Timer error is gone Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6adf71479c30f5b6751a21edc4bfa311ddbef5ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-03mb/google/zork: Add HID for max98357aRaul E Rangel
The default HID was removed by a1c82c5ebee. We need to explicitly specify it. BUG=b:154756391 TEST=No longer see ERROR: _HID required message in console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-03drivers/generic/max98357a: Don't write device if HID is missingRaul E Rangel
If the device is missing the HID, the code would previously leave an open scope and device on the stack. BUG=b:154756391 TEST=Verify stack ACPI stack does not exceed limit on Trembyle. Fixes: a1c82c5ebee ("drivers/generic/max98357a: Allow custom _HID from config") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03soc/amd: Use mp_cpu_bus_init()Kyösti Mälkki
Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-03soc,southbridge/amd: Remove some explicit zero-initializersKyösti Mälkki
Change-Id: I263c159fe4b7757dd5abfc0d6248e45b749df980 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetreeArthur Heymans
These devices never show on the PCI domain. Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/gigabyte/ga-g41m-es2l: Add PEG to devicetreeArthur Heymans
Change-Id: Icebf0eea4e1fee6d15ba3f1a080cbc40b42fd733 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03soc/intel/quark/memmap: Add missing 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
Change-Id: I6a066659758aeb0251d9b37f525ad987b90832db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41787 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in ↵Furquan Shaikh
hostbridge.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-03northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntaxFurquan Shaikh
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link. Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-03northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in ↵Furquan Shaikh
hostbridge.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-03northbridge/intel/haswell: Update hostbridge.asl to ASL2.0Furquan Shaikh
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/beltino. Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-03soc/intel/jasperlake: Update C-States infoRonak Kanabar
- Update C-States max latency values - Remove MSR programming for C-States latency BRANCH=None TEST=Boot to OS and check CState Latenecy >cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency} POLL C1_ACPI C2_ACPI C3_ACPI 0 1 253 1048 Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03soc/tigerlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03mb/aopen/dxplplusu: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Board does not support ACPI S4 or C-states or P-states. Change-Id: If83efb72e076d404468259e312a5afac625f04af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03Makefile: Drop HAVE_SMI_HANDLER test for smm-classKyösti Mälkki
Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubsKyösti Mälkki
Board does not have ChromeEC. Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC testsKyösti Mälkki
Boards have unconditional select EC_GOOGLE_CHROMEEC. Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03acpi: Drop typoed __ROMC__Kyösti Mälkki
Change-Id: I4fcec5bbc038a31565882631052ab07e38946e65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-03mb/bap/ode_e21XX: Drop old commented KconfigsKyösti Mälkki
Change-Id: I56225c0a533e5f9e8294b7866a41c9a6c24a7f67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03mb/google/zork: Delete sb_fch.aslRaul E Rangel
This file is not used. BUG=b:154756391 TEST=Build trembyle and check that peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03soc/amd/picasso/acpi: Add missing eMMC deviceRaul E Rangel
BUG=b:154756391 TEST=Boot trembyle and see that /dev/mmcblk1 now exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 00:15:28 +0000