Age | Commit message (Collapse) | Author |
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All callers of locate_vbt just care about the file content and
immediately map the rdev for its content.
Instead of repeating this in all call sites, move that code to
locate_vbt.
Change-Id: I5b518e6c959437bd8f393269db7955358a786719
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When reusing the same image across multiple devices, they sometimes need
different VBTs, so provide a hook for mainboard code to specify which
file is required.
Change-Id: Ic7865dc0e0c9ea3077b749d9d0482079877e9c4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable MRC cache by default.
TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.
Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Reduce the bootblock size to 16KiB from the default 64KiB.
Not all that space is necessary.
Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The src/soc/intel/common/basecode/Kconfig path does not exist.
Remove the inclusion of the invalid path.
Change-Id: Icbd8f310cad4246b72bc869bcf4a089ae2f0c5a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Try restoring previous memory training results from SPI flash
to improve raminit speed.
Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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No need for having two of everything in the coreboot codebase.
Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add all the SOC level DSDT tables, reference from skylake/kabylake.
Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20499
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch helps managing power state variables from within the
library. Adds migrate_power_state which migrates the chipset
power state variable, reads global power variable and adds it
in cbmem for future use. This also adds get_soc_power_state_values
function which returns the power state variable from cbmem or
global power state variable if cbmem is not populated yet.
Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The amdfwtool now outputs firmware that is correctly built for the
new location.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it
needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used.
Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix issues reported by coverity scan in the below files.
src/soc/intel/common/block/i2c
1375440: Improper use of negative value
1375441: Improper use of negative value
1375444: Improper use of negative value
src/soc/intel/apollolake/i2c.c
1375442: Unsigned compared against 0
Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Config for activating VR mailbox command for Intersil VR C-state issues.
0 - no mailbox command sent.
1 - VR mailbox command sent for IA/GT rails only.
2 - VR mailbox command sent for IA/GT/SA rails.
BUG=b:65499724
BRANCH=none
TEST= build and boot soraka.
Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSP header files to version 2.7.2.
New UPDs added
FspmUpd.h:
*CleanMemory
FspsUpd.h:
*IslVrCmd
*ThreeStrikeCounterDisable
Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.
CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.
Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.
Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Note: For some of the boards affected ACPI S3 support
was never tested but feature was just copy-paste from
reference design.
Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.
BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.
Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update FSP header file to latest version, cannonlake reference code
7.0.14.11. Details of FSP changes can be find in FSP release notes.
Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already
includes this.
Change-Id: Ib2de0f384a547240528b18f07327566354164699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Boot to OS
Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21758
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable CPU Ratio override as input to FSP Memory init.
Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add ACPI methods for gpio, scs and pcr.
TEST=Boot to OS.
Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI dsdt table for northbridge, report proper resources in dsdt
entries.
TEST=Boot up into OS fine.
Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Include SMI Handler support for Cannonlake RVP platform.
Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1.Add common ITSS support as part of LPC driver init code.
2.Add LPC pci driver for CNL
Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable Skylake to use the new common LPC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add support for following functionality:
1. Set up PCH LPC interrupt routing.
2. Set up generic IO decoder range settings.
3. Enable CLKRUN_EN for power gating LPC.
Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used
in Stoney Ridge, so get rid of them.
Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Allow the AMD FW directory to be placed at one of the alternative
locations within the ROM.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.
TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.
Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The Stoney Ridge UART and AMBA devices must be powered and report power
and clock OK prior to using the coreboot serial console. The code used
to have a delay to wait for the power and clock, but didn't check the
OK bits. This caused long delays on a reboot, as each byte would time out
until the console was reset again at romstage.
This change also removes the UART reset. The device has just been
powered and is in reset already. Testing indicates the reset isn't
needed.
BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.
Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Half the files were being placed in build/agesa and half in
build/libagesa.
Change-Id: Ied69dafffe2eb3354bd430789e098a1cb1d40551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove no-op statements and code-rephrasing comments, apply some cosmetic
changes to improve readability.
Change-Id: I124a6bc338c2589fab66ca91bf53139b4413d10b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix boot regression after commit
d4955f0 AGESA: Move API interface under drivers/
Boards were left without cache-as-ram setup code
and appeared completely dead.
Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
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Do not check for the top of memory being 16MB-aligned near the end of
romstage. This is not the expected alignment using the default 8MB SMM
region size.
BUG=b:67320715
Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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This patch moves the functions update_pm1_enable and read_pm1_enable
to common block PMC. We rename the functions to pmc_update_pm1_enable and
pmc_read_pm1_enable to keep semantics consistent.
Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.
Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the APMC-specific initialization call. Make the function
which programs the event type not static and call it from the
southbridge.c file.
Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Rewrite the handler to be more compact and extendable. The old
functionality is duplicated after the rewrite. All SMI source registers
(except for SmiSciStatus) behave identically so these are consolidated.
Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on.
Create a table of mini-handlers to be supported in the soc directory.
As SMI sources are discovered, attempt to find the corresponding handler
and then execute it.
Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Replace hardcoded values with defined ones.
Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Use the currently programmed address of the SMI command port before
checking the passed command. This ensures we're reading the right
port in case the port was relocated without our knowledge.
Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Pull all pm_read and write, smi_read and write variants into a single
file.
Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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