summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-01-16drivers/spi/spi_flash: separate out protection opsAaron Durbin
Put the write protection into its own object. This allows for easier future reuse of objects in future consolidation patches. It's also possible to eliminate the code implmementing these in the future if the platform doesn't require it. For now leave current behavior as-is. The names of the callbacks were shortened as they are now in the spi_flash_protection_ops object which is a new field in the spi_flash object. Change-Id: I2fec4e4430709fcf3e08a55dd36583211c035c08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16drivers/spi/spi_flash: assume spi_flash read callback existsAaron Durbin
spi_flash_erase() and spi_flash_write() already assume their respective callbacks are supplied in the spi_flash_ops object. Make the same assumption in spi_flash_read(). In order to do this the spi_flash_ops objects from the drivers need to reference the the previously used fallback read command, spi_flash_read_chunked(). This function is made global and renamed to spi_flash_cmd_read() for consistency. By doing this further dead code elimination can be achieved when the spi flash drivers aren't included in the build. A Hatch Chrome OS build achieves a further text segment reduction of 0.5KiB in verstage, romstage, and ramstage. Change-Id: I7fee55e6ffc1983657c3adde025a0e8c9d12ca23 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
This patch doesn't change the resulting binary of a timeless build. Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
This is to get a uniform format that matches the macros added in the next patch, so that said follow-up patch won't change the output binary. lenovo/x230 still boots with this patch. Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft resetPiotr Kleinschmidt
LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15superio/nuvoton/nct5104d: Add soft reset GPIO functionalityPiotr Kleinschmidt
So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOs are not in unknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15soc/intel/common/block/fast_spi: don't include all spi flash driversAaron Durbin
The fast spi driver implements hardware sequencing which abstracts away the underlying spi flash commands in the hardware block. It also has its own spi flash probe function to intercept the spi flash ops. As such it's not necessary to include all spi flash drivers. On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage, romstage, and ramstage. Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15drives/spi/spi_flash: add option to not select all driversAaron Durbin
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS, to make it easier for other parts of the code base to indicate that all spi flash drivers should not be included. Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15soc/intel/tigerlake: Update header filesRavi Sarawadi
Modify header files to update/include tigerlake: - IOMAP BARs according to silicon reference code - Update Serial IO devices according to PCH EDS - Add board types BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held
LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order of computation, so that the big refactoring doesn't change the output binary of a timeless build. Now this workaround can be dropped. Tested on lenovo/x230: still boots Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15mb/google/slippy: update VBTMatt DeVillier
The current BIOS-extracted VBT breaks backlight control with Tianocore, so replace it with one that does. Settings were exported using Intel BMP tool and the overlayed onto a GOP-format (vs BIOS format) VBT file. Test: boot google/wolf with both SeaBIOS and Tianocore payloads, verify backlight control functional under both Linux and Windows. Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-15nb/intel/sandybridge: Repurpose HOST_BRIDGE macroAngel Pons
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be replaced with config_of_soc() in a follow-up. Tested with BUILD_TIMELESS=1, resulting binary is identical. Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/google/dedede: Add dedede mainboardKarthikeyan Ramasubramanian
Add mainboard stubs for Dedede. More functionalities will be added later. BUG=b:144768001 TEST=Build test. Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/intel/tglrvp: Update KconfigWonkyu Kim
Updating Kconfig to add Chrome OS support with both internal and external EC BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia63c06e3b4b4effcace7a8458b1066a615de2008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38148 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/intel/tglrvp: Add initial mainboard codeRavi Sarawadi
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Tigerlake". 2. Replace "icelake_rvp" with "tglrvp". 3. Rename "icl" with "tgl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake". 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add board support namely BOARD_INTEL_TGLRVP_UP3 10. Replace icl_u and icl_y variant with tglrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per tigerlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 32MB BIOS region. 5. clean up and make empty devicetree setting TEST=Build tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-14mb/google/kukui: Support panels using ANX7625Hung-Te Lin
For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-14mb/google/drallion: Enable dynamic sarEric Lai
Drallion will use two sar table for tablet and clam shell mode. BUG=b:140469407 TEST=Build and check the config has enable BRANCH=none Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0367741e795a3b00c490ecb1972d22b9f454134f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-01-14sb/intel/i82371eb: Add PIIX4 definitionsKeith Hui
These new definitions will be used by two other changes. Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUSKyösti Mälkki
Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38236 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14intel/nehalem,ibexpeak: Move enable_smbus() callKyösti Mälkki
Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/sandybridge,bd82x6x: Move enable_smbus() callKyösti Mälkki
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() callKyösti Mälkki
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14intel/{i945,pineview},i82801gx: Move enable_smbus() callKyösti Mälkki
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14drivers/pc80/rtc: Clean up some POST_CODE_EXTRA useKyösti Mälkki
Change-Id: I5ecfa0860a28547f76a72592a8d07bca67822217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38188 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14console/post: Split parts to arch/Kyösti Mälkki
Both IO port and cmos are currently arch/x86 only features. Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14nb/intel/sandybridge: Drop 'or zero' instancesAngel Pons
Change-Id: Icd0dfdf311ac141992ec6a6026ca92e54e8d2094 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-14soc/intel/cannonlake: Fix ASL compilation remarksSubrata Banik
This patch fixes below ASL compilation remarks 1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13vc/amd/agesa: Fix out of bounds readJoe Moore
ByteLane is used unitialized from prior for statement, creating a potential out-of-bound read of RxOrig[MaxByteLanes]. PassTestRxEnDly[MaxByteLanes] never appears as rvalue; all for loops have ByteLane < MaxByteLanes exit condition. Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-01-13mb/packardbell/ms2290/acpi_tables: Remove unneeded includesElyes HAOUAS
Change-Id: Iba380cf96991c9e1fec96aa3d793818524388897 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/lenovo/thinkcentre_a58/acpi_tables: Remove unneeded includesElyes HAOUAS
Change-Id: I8f8e43d0f146b1050eb68da197504441b60a4120 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/intel/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I3b110ab749992d1c1793b1d4de43c1d2e8ca15ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asus/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Iba39673a81f235204d6ae9fe9e18239e5b81b17f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/gigabyte/ga-g41m-es2l/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I4b3b2d801698305dc6c214c58d367772ea2096a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/gigabyte/ga-b75m-d3h/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Ic94e60188dbb9cdee959ecfa5ef14c92f125e3f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I41e3cbb4fbdd6680c1d9d347efc35d1618233a64 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asus/p8z77-m_pro: Fix typosElyes HAOUAS
Change-Id: I3c63ca745bf10ec0b0c4cef898db3f7ebfee5bde Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38364 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-13mb/asrock/imb-a180: Fix typoElyes HAOUAS
Change-Id: Iff032a321301772789a42f29cfc187c446b4cfa1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13arch/x86/cf9_reset: Fix typoElyes HAOUAS
Change-Id: I4a8d29ab647837965e5341d019664f0ed401639a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13arch/x86: Fix typosElyes HAOUAS
Change-Id: I944b9bf8f518eff9b539769825174bf1544e6b34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/facebook/monolith: Enable SpeedStep and DPTFWim Vervoorn
BUG=N/A TEST=tested using fwts on facebook monolith. Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-13ec/lenovo/h8: Prepend EC log message with *H8*Paul Menzel
All other messages in `ec/lenovo/h8` are prepended with *H8*, so also prepend the EC version log message with *H8*. EC Firmware ID 79HT50WW-3.4, Version 7.01A No CMOS option 'usb_always_on'. H8: BDC detection not implemented. Assuming BDC installed H8: WWAN detection not implemented. Assuming WWAN installed No CMOS option 'fn_ctrl_swap'. Change-Id: Ib4f341946a336b57bd96c053a05364276caad1ac Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-01-12mb/*/*: use ACPIMMIO common block wherever possibleMichał Żygowski
TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-12include/arch/romstage: Fix typoElyes HAOUAS
Change-Id: Ie0c80792210ded7f81184b60ba2b0b51c13db283 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12include/arch/acpigen: Fix typoElyes HAOUAS
Change-Id: I277d4a36f3d76ff5e12f255165e2b08480c39167 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12soc/intel: Fix ACPI device operations initializationKarthikeyan Ramasubramanian
Initialize ACPI device operations only when CONFIG_HAVE_ACPI_TABLES is enabled. BUG=None TEST=Build Test Change-Id: I5c5266885d8b08338d17a87bb95110765882120e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-06 21:02:17 +0000