summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2015-01-04ipq806x: move GPIO definitions to the proper include fileVadim Bendebury
When the IPQ SPI driver was ported to coreboot, a few GPIO related definitions ended up in a wrong include file. Move them to the proper place and get rid of duplicated definition of GPIO_OUT. BUG=chrome-os-partner:27784, chrome-os-partner:29871 TEST=proto0 still boots with the new firmware Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4 Reviewed-on: http://review.coreboot.org/8058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04ipq806x: move translation table out of the wayVadim Bendebury
Depthcharge clears up all unused DRAM before starting Linux, and does not know the translation table location. Instead of adding an exclusion term to the memory wipe descriptor let's move the table to the top of IMEM, it is also likely to be a good location in the future, when EFS is introduced. BUG=chrome-os-partner:27782 TEST=manual . built and ran firmware on ap148 Original-Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203624 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 4250f8574d6cc0bbec5ba0411f22d801f034afb8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I12cd74e3d318b878e7703414a7ddaaed0812cb7a Reviewed-on: http://review.coreboot.org/8057 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-04ipq806x: Add USB supportJulius Werner
This patch adds code to initialize the two DWC3 USB host controllers and their associated PHYs to the IPQ806x SoC (closely imitating the existing DWC3 implementation for Exynos5), and uses them to initialize USB on the Storm mainboard. BUG=chrome-os-partner:29375 TEST=Hack up netboot to get around missing SPI flash, load a file over TFTP. Hack a storage read into the storage attach function, dump the data and confirm that it looks right. Enable USB debugging and confirm 3.0 devices get enumerated at SuperSpeed (mostly). Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202157 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af Reviewed-on: http://review.coreboot.org/8056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04nyan_big: Update Hynix BCTs and add Kingston 2GB BCT.Tom Warren
Hynix 2GB/4GB configs have been fine-tuned. Kingston 2GB config is new, uses RAMCODE 0x6. BUG=none TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my Big 2GB system (PVT1/SKU1) and it booted OK. BRANCH=nyan_big Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203305 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd Reviewed-on: http://review.coreboot.org/8045 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04tegra124: configure DP with correct pixel clockVince Hsu
For some panels, the plld can't provide the pixel clock that the panels wants, so we give it a good enough one. And we should calculate the dp/dc settings by the real pixel clock. BRANCH=nyan BUG=chrome-os-partner:29489 TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big). No screen flicker is observed. No sor dp fifo underflow found. Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779 Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203358 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac Reviewed-on: http://review.coreboot.org/8044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04arm: lpae: Set XN and PXN bits for noncacheable regionsJimmy Zhang
Add XN/PXN bits to prevent cpu from fetching speculative instructions on noncacheable region. BUG=chrome-os-partner:28568 BRANCH=nyan TEST=Build and run reboot tests on nyan_big Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b Original-Reviewed-on: https://chromium-review.googlesource.com/203447 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe Reviewed-on: http://review.coreboot.org/8043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04nyan: Ignore the recovery GPIO.Todd Broch
CrOS devices with Chromeos EC need only use hostevent to communicate recovery assertion to the BIOS. This CL removes wired GPIO from determining recovery as it appears under certain conditions (cold reset) the internal PU on the AP isn't strong enough and therefore the value is sometimes seen as asserted. BRANCH=none BUG=chrome-os-partner:29333 TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot. Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2 Original-Signed-off-by: Todd Broch <tbroch@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202996 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f Reviewed-on: http://review.coreboot.org/8042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04samus: Minor fixes for P1.9 boardsDuncan Laurie
- Put SSD into reset on transition to S3/S5 to prevent leakage - Fix GPIO number for wlan disable used in smihandler - Enable generic hub driver in libpayload - Fix comment in devicetree about S0ix BUG=chrome-os-partner:28502 BRANCH=None TEST=Build and boot on samus Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203185 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0 Reviewed-on: http://review.coreboot.org/8048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04wtm2: Fix issues with USB in firmwareDuncan Laurie
XHCI driver was not enabled in libpayload and some ports were disabled that should be enabled. The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to properly indicate unused so crossystem does not attempt to export GPIO number 255 in the kernel and trigger a warning. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/203184 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 328362469b00c9467908a7d18a031fee73753def) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434 Reviewed-on: http://review.coreboot.org/8047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-04samus: Enable DDI2 hotplugDuncan Laurie
Both DDI ports may be used on this board so it needs to be able to detect a device on either port. BUG=chrome-os-partner:28234 TEST=None (needs hardware) Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202358 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099 Reviewed-on: http://review.coreboot.org/8046 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-04samus: Update for board revision 1.9Duncan Laurie
- Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 Reviewed-on: http://review.coreboot.org/8007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04samus: Move SPD related information to spd directoryDuncan Laurie
Put all the SPD related information in one place including the onboard SPD sources and the board specific parsing. BUG=chrome-os-partner:28234 TEST=Build and boot on samus Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201082 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123 Reviewed-on: http://review.coreboot.org/8006 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04wtm2: Convert to use soc/intel/broadwellDuncan Laurie
Convert wtm2 board to use the broadwell soc chipset. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 with haswell and broadwell CQ-DEPEND=CL:201067 CQ-DEPEND=CL:*164226 Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201070 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda Reviewed-on: http://review.coreboot.org/8001 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-03intel/model_206ax: update microcodeNicolas Reinecke
tested on ivy and sandy (t520/t420s & t530) Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7976 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03ipq806x: clean up UART driver tx_byte functionVadim Bendebury
The driver as it was copied from u-boot provided a function to transmit multiple characters in one invocation. This feature was not ported to coreboot, there is no need to maintain the complexity when only one character at a time is transmitted. It is also very desirable to get rid of a 1024 byte array allocated on the stack. The array was necessary to allow to convert multiple newline characters in the transmit data flow into two character sequences CRLF. Now just a single word is enough to keep one or two characters to transmit. [EDIT km: newline translation is now part of printk] BUG=chrome-os-partner:27784 TEST=verified that coreboot with the new code prints generates console output. Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201782 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8011 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03ARM64: Always has DYNAMIC_CBMEMKyösti Mälkki
The static allocator only worked for x86 anyway. Change-Id: Ibe4e172bb654f6414949bd11787c9407d091a858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8028 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03ARMv7: Always has DYNAMIC_CBMEMKyösti Mälkki
The static allocator only worked for x86 anyway. Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8030 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03storm: Put the page table at a correct addressVadim Bendebury
The recently introduced page table location value is wrong, it overlaps with other areas of the code. This patch fixes the location, a more robust scheme is needed for memory layout management. BUG=none TEST=manual . occasional random failures disappear after this patch is applied Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202641 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7afcab42db259e53541fb991b36d680fc2186304 Reviewed-on: http://review.coreboot.org/8019 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-03storm: modify memory layoutVadim Bendebury
This is an interim change (before EFS is enabled), align ROM and RAM stages so that they have enough room and do not step over each other. BUG=chrome-os-partner:27784 TEST=manual . booted coreboot successfully on ap148 Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202046 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481 Reviewed-on: http://review.coreboot.org/8012 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-03mainboard/storm: setup mmu in storm mainboard_initDeepa Dinamani
enable protection of zero page access, provide for uncached device memory range, and protect against access outside of DRAM except to device registers. BUG=chrome-os-partner:28467 TEST=verified mmu.pagetable.list output: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--000FFFFF| | | | | | | | | C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200341 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/mainboard/google/storm/mainboard.c Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1 Reviewed-on: http://review.coreboot.org/8010 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.Deepa Dinamani
Define a base address for page table entries. Place it 64KB below the bootblock loading address. BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled. Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200332 (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068 Reviewed-on: http://review.coreboot.org/8009 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03ipq8064: add SOC initialization skeletonVadim Bendebury
The main benefit of adding this skeleton is the addition of the correct memory map to CBMEM. Attempts to load depthcharge do not fail because of unavailability of the bounce buffer. BUG=chrome-os-partner:27784 TEST=boot updated firmware on AP148, observe CPU: Qualcomm 8064 in the ramstage console output as well as not failing to load depthcharge any more. Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199675 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013 Reviewed-on: http://review.coreboot.org/8000 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-03storm: enable early consoleVadim Bendebury
Include the required modules in romstage and enable early console. BUG=chrome-os-partner:27784 TEST=observe the romstage prompt in the console output: coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting... Original-Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6e643d3425ee226b3ebfbf329b35e7017f83d0c3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibdc695da634356988b3e551b0a9e4be2e129ccb4 Reviewed-on: http://review.coreboot.org/7997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03storm/ipq8064: add dynamic CBMEM supportVadim Bendebury
Squashed the correction patch with the original to avoid confusion in coreboot.org review. All what's needed apart from configuring the feature is to provide a function which would report the top of DRAM address. BUG=chrome-os-partner:27784 TEST=manual . with all other patches applied, the image proceeds all the way to trying to download 'fallback/payload'. Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3 Original-Reviewed-on: https://chromium-review.googlesource.com/197897 (cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> storm: initialize dynamic cbmem properly Dynamic cbmem support has been enabled on storm, but the proper initialization at romstage is missing. Proper DRAM base address definition is also necessary so that CBMEM is placed in the correct address range (presently at the top of DRAM). BUG=chrome-os-partner:27784 TEST=build boot coreboot on ap148, observe the following in the console output: Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5 coreboot table: 256 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199674 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74 Reviewed-on: http://review.coreboot.org/7996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03ipq8064: Configure storm bootblock to runVadim Bendebury
This adds necessary configuration options to enable bootblock on Storm to read the rombase image from the SPI flash. BUG=chrome-os-partner:27784 TEST=manual . after this change is applied, the AP148 boots coreboot from the Spansion SPI flash device: coreboot-4.0 Thu May 1 14:25:34 PDT 2014 starting... Exception handlers installed. SF: Detected S25FL128S_256K with page size 10000, total 2000000 CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001 coreboot-4.0 Thu May 1 14:25:34 PDT 2014 booting... Exception handlers installed. ... Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197801 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67 Reviewed-on: http://review.coreboot.org/7995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03lenovo/t420s: Add new port.Nicolas Reinecke
This is based on x220 and t520. Tested on i7 model with usb3. There is no support for nvidia gpu and optimus. Change-Id: I6ca9436ccec3024095d02078e5e450147841e463 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7974 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-01-03blaze: change ramcode 1000/1001/1010 to use 792MHz bctNeil Chen
This change updates the cfg file for Hynix/Micron/Samsung 4GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202059 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c Reviewed-on: http://review.coreboot.org/8008 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-01-03storm: ipq8064: enable CBFS SPI wrapperVadim Bendebury
This change forces storm platform to use the common CBFS SPI wrapper, which makes the SOC specific CBFS code unnecessary and requires including SPI controller support in all coreboot stages. BUG=chrome-os-partner:27784 TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197932 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2 Reviewed-on: http://review.coreboot.org/7994 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03ipq8084: provide monotonic us timerVadim Bendebury
This service is required by various coreboot code modules. It looks like the 8064 SOC does not provide anything better than a 32 KHz free running counter (it is used in u-boot for us timer as well). Let's use this for now. BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to start the payload. Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197896 (cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id37ed21193db67ceee11a795713c34ef26383380 Reviewed-on: http://review.coreboot.org/7993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03arm: Fix stored PC value when handling exceptionsJulius Werner
ARM processors save the PC value in the Link Register when they handle and exception, but they store it with an added offset (depending on the exception type). In order to make crashes easier to read and correctly support more complicated handlers in libpayload, this patch adjusts the saved PC value on exception entry to correct for that offset. (Note: The value that we now store is what ARM calls the "preferred return address". For most exceptions this is the faulting instruction, but for software interrupts (SWI) it is the instruction after that. This is the way most programs like GDB expect the stored PC address to work, so let's leave it at that.) Numbers taken from the Architecture Reference Manual at the end of section B1.8.3. BRANCH=none BUG=chrome-os-partner:18390 TEST=Provoked a data abort and an undefined instruction in both coreboot and depthcharge, confirmed that the PC address was spot on. Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199844 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6 Reviewed-on: http://review.coreboot.org/7992 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-03elog: Add function to log boot reason in ChromeOS caseDavid Hendricks
This adds a generic helper function for adding boot reason in the ChromeOS case. If vboot is enabled, it will use information passed in via the vboot handoff table in cbmem to determine mode and reason in the case of recovery. BUG=chromium:373467 BRANCH=nyan TEST=built along with follow-up CL and booted on Big under various modes, verified entry was added to eventlog with "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b Original-Reviewed-on: https://chromium-review.googlesource.com/199690 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75 Reviewed-on: http://review.coreboot.org/7991 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-02allwinner/a10: Always has DYNAMIC_CBMEMKyösti Mälkki
The static allocator only worked for x86 anyway. Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8029 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-02Allow RISCV to be compiled with ANY_TOOLCHAINRonald G. Minnich
Change-Id: I9210241c902ad8a88980a7c9cdb0d52c460b2541 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/8025 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-01-01soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.Ronald G. Minnich
riscv builds again. Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/8026 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-01ARM: Fix ARM_LPAE to not be selectable as a menu item.Ronald G. Minnich
It was showing up as a menu item and it should not. Change-Id: I448f683fbf4187b11821381332f971b1daea29f8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/8027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-01mainboard/lenovo/t530/Kconfig: Enable VMX by defaultEdward O'Callaghan
Fix a trivial tab/space indent inconsistency while here. Change-Id: I819d85293e1a070817cd13349a220ba85ba89951 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-31samus: Combine mainboard patches to build soc/intel/broadwellDuncan Laurie
Combine four patches dependencies. These will not build individually, so combine them for coreboot.org upstream. samus: Move SPD handling to separate file The code to find the SPD data for the mainboard based on GPIOs is moved from romstage.c into spd.c. It relies on the updated pei_data structure from broadwell instead of the haswell interface. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Move PEI data structure init to separate file This needs to be executed in both romstage and ramstage for the different PEI binary stages. It uses the broadwell interface now instead of haswell. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199921 (cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Convert mainboard to use soc/intel/broadwell Switch from the haswell cpu/northbridge/southbridge interface to the soc/intel/broadwell interface. - Use new headers where appropriate - Remove code that is now done by the SOC generic code - Update GPIO map to drop LP specific handling - Update INT15 handlers, drop all but the boot display hook BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199922 (cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Add some code to print basic info from SPD The handling of LPDDR is a bit messy in Intel platforms. There is no traditional SPD so instead one is created by hand from the provided datasheets. These have varying (and sometimes unexpected) geometry and it can be important during bringup to know what configuration is being passed to the memory training code. This could in theory be put in a more generic location, but for now this is the only board with LPDDR3 where I have found it valuable. BUG=chrome-os-partner:28234 TEST=Build and boot on samus, look for SPD details on the console. CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199923 (cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d Reviewed-on: http://review.coreboot.org/7943 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31broadwell: Hook into the build systemDuncan Laurie
Hook the soc/intel/broadwell directory into the configuration and build system so it can be used by mainboards. BUG=chrome-os-partner:28234 TEST=build and boot on wtm2 Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b Reviewed-on: http://review.coreboot.org/7940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31broadwell: Preparations for buildingMarc Jones
Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-31ipq8064: modify SPI controller driver to work in corebootVadim Bendebury
A typical SPI operation consists of two phases - command and data transfers. Command transfer is always from the host to the chip (i.e. is going in the 'write' direction), data transfer could be either read or write. We don't want the receive FIFO to be operating while the command phase is in progress. A simple way to keep the receive FIFO shut down is to not to enable it until the command phase is completed. Selective control of the receive FIFO allows to consolidate the receive and transmit functions in a single spi_xfer() function, as it happens in other SPI controller drivers. The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the next byte can be written or received, respectively. While data is being received the 0xFF bytes are transmitted per each received byte, to keep the SPI bus clocking. The data structure describing the three GSBI ports is moved from the .h file into .c file. A version of the clrsetbits macro is added to work with integer addresses instead of pointers. BUG=chrome-os-partner:27784 TEST=not yet, but with the res of the changes the bootblock loads and starts the rombase section successfully. Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197779 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f Reviewed-on: http://review.coreboot.org/7983 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-12-31ipq8064/storm: UART enable and various fixesVadim Bendebury
The original patch from chromium was a bit of a mishmash. Between that, rebasing and using the coreboot.org UART infrastructure, the patch has changed a bit from the original. It seems reasonable to keep these changes together. - build in the ipq UART and turn on bootblock console - sets LPAE and ROM header address - adds cpd.c to storm The original commit: ipq8064: make UART driver work in bootblock This patch it the last one in the chain adapting the ipq9064 UART driver for use in coreboot. A new config option (CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of the driver. The previously introduced uart_wrapper.c is now included in the build to provide the console driver structure used by ramstage. Necessary configuration options are added to allow use of UART in the bootblock. BUG=chrome-os-partner:27784 TEST=with this change the coreboot image on AP148 prints a banner on start up: coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting... Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196663 (cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91 Reviewed-on: http://review.coreboot.org/7875 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-31vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistentEdward O'Callaghan
Change-Id: I41ba4cffa545a31c1e0845ec44c8a433bda9f99d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7886 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31arch/x86: Declare GDT symbols and move_gdt()Kyösti Mälkki
We relocate GDT to CBMEM, this can be done late in ramstage. Note: We currently do this for BSP CPU only. Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7858 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31Fix Kconfig whitespaceKyösti Mälkki
Change-Id: Iad64d018edda3064a77bfbcd41cfea5275a2e737 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8013 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31baytrail: add more gpio init macrosKane Chen
GPIO init marcos are not enough to initialize different gpio attributes BUG=none TEST=emerge-rambi coreboot works well Original-Change-Id: I193fa7b3e22632cacb555e726e3dd3991f4f4faa Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200531 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5e0fcbcd7cefcfccb5b565003336d197bb29e4cc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6bf4db9397733a003dfdedc6eb63b82127917851 Reviewed-on: http://review.coreboot.org/7953 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31nyan*: Set GEN2 I2C pads to open-drain modeKen Chang
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus the pinmux E_OD bit of these two pins needs to be set to ensure GEN2 I2C pads work fine on 3.3V. BRANCH=nyan BUG=none TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c on blaze w/o this change. the waveform looks good on both scl/sda pins w/ this change. Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200996 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea Reviewed-on: http://review.coreboot.org/7952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31Print segment clean up information only when required.Vadim Bendebury
Eliminate duplicated printout and if needed, print only changed information. BUG=none TEST=verified that the 'New segment dstaddr...' message is not duplicated anymore Original-Change-Id: Ia13593394fccbb225f2bd9ab2b9228bac29d50fb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199672 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit aadf018821ebfa63d6ac9d2429ae1fb483dd6cb3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7544bddc4026191395cfe3b8ac66256ec223391e Reviewed-on: http://review.coreboot.org/7937 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-31rambi: Add _PRW for LID0 ACPI DeviceShawn Nematbakhsh
The kernel will not track wakeup events for devices unless they have a defined _PRW. There is no EC output of the lid signal coming to a GPIO and instead it pulses PCH_WAKE#. BUG=chrome-os-partner:27631 TEST=Manual on Rambi. - Run lidclose + lidopen on EC console, verify that wakeup_count increments. - Run lidclose + lidopen in rapid succession, verify that suspend request is aborted. BRANCH=Rambi. Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200289 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a Reviewed-on: http://review.coreboot.org/7945 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31rambi: Unconditionally clear the EC recovery requestSheng-Liang Song
Implement Rambi clear_recovery_mode_switch() BUG=chromium:279607 BRANCH=TOT TEST=Verified recovery sequences on Rambi. Original-Change-Id: I481329d0f49584ad0314bd982b80bbc86112c2c0 Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197781 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Commit-Queue: Sheng-liang Song <ssl@google.com> Original-Tested-by: Sheng-liang Song <ssl@google.com> (cherry picked from commit 77e60a039f3d8328694a743e7cd15cce71b02f5d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I837151551b8aa68cf86b6fa1dd39b7b673d6a4d9 Reviewed-on: http://review.coreboot.org/7896 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-12-30chromeos: Unconditionally clear the EC recovery requestSheng-Liang Song
Add the empty weak function clear_recovery_mode_switch(). Problem: If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set, the following will happen: 1. Boot device in recovery mode with Esc + F3 + Pwr. 2. Turn device off with Pwr button. 3. Turn device on with Pwr button. Device still boots to recovery screen with recovery_reason:0x02 recovery button pressed. If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the device off and on again with the Pwr button does a normal boot. Solution: Unconditionally clear the recovery flag. BUG=chromium:279607 BRANCH=TOT TEST=Compile OK. Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197780 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Commit-Queue: Sheng-liang Song <ssl@google.com> Original-Tested-by: Sheng-liang Song <ssl@google.com> (cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae Reviewed-on: http://review.coreboot.org/7895 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 18:25:32 +0000