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2018-08-10arm64: Drop checks for current exception level, hardcode EL3 assumptionJulius Werner
When we first created the arm64 port, we weren't quite sure whether coreboot would always run in EL3 on all platforms. The AArch64 A.R.M. technically considers this exception level optional, but in practice all SoCs seem to support it. We have since accumulated a lot of code that already hardcodes an implicit or explicit assumption of executing in EL3 somewhere, so coreboot wouldn't work on a system that tries to enter it in EL1/2 right now anyway. However, some of our low level support libraries (in particular those for accessing architectural registers) still have provisions for running at different exception levels built-in, and often use switch statements over the current exception level to decide which register to access. This includes an unnecessarily large amount of code for what should be single-instruction operations and precludes further optimization via inlining. This patch removes any remaining code that dynamically depends on the current exception level and makes the assumption that coreboot executes at EL3 official. If this ever needs to change for a future platform, it would probably be cleaner to set the expected exception level in a Kconfig rather than always probing it at runtime. Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Remove set_cntfrq() functionJulius Werner
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10marvell: Remove 'mvmap2315' SoCJulius Werner
I'm pretty sure this SoC doesn't actually exist. Change-Id: I53e268ee1795e524a2a4562d67a2b9f28af966d1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10google: Remove board 'rotor'Julius Werner
Rotor is dead, long live [PROJECT NAME REDACTED]! Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27964 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: add support for fetching DRAM part number from CBIAaron Durbin
Add 3 new Kconfig options: DRAM_PART_NUM_IN_CBI DRAM_PART_NUM_ALWAYS_IN_CBI DRAM_PART_IN_CBI_BOARD_ID_MIN These control whether to 1. attempt to use CBI at all 2. always use cbi and 3. conditionally use cbi based on board id. The intent is that the MIN variant would be used for the tranisition period then cut over to ALWAYS after full transition. Since multiple OEMs have different schedules these options are there to bridge the gap. yorp. bip, and octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case someone does the MIN values are 255 to always take the old path. BUG=b:112203105 TEST=Set correct part number on phaser during testing. Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09arch/x86/tables.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure arch_write_tables, the pointer "rom_table_end" is updated every time a table is created. However, after creating last table, pointer rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09cpu/x86/mp_init.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure save_bsp_msrs, the structure pointer "msr_entry" is updated every time procedure save_msr() is called. However, after the last call of save_msr(), "msr_entry" is not used, thus causing a static analysis error. Add a "(void)msr_entry;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0fb336fbf49eec3da255fadbe38b3a38768d0cf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/cpu: Fix typoElyes HAOUAS
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device: Fix typoElyes HAOUAS
Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/ec/google/chromeec: Fix typoElyes HAOUAS
Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/include: Fix typoElyes HAOUAS
Change-Id: Iff445dccf29957078b8308d73fb302d03cf47d31 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/lib: Fix typoElyes HAOUAS
Change-Id: Ie5bf036a63a254dd95b45a0823086c8079eeafe2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/arch: Fix typoElyes HAOUAS
Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/security/vboot: Fix typoElyes HAOUAS
Change-Id: Ie98ee00a83d837b6d6491fed3a474048dc23e104 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/superio: Fix typo and remove unneeded whitespaceElyes HAOUAS
Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09google/grunt: Override BayHub EMMC driving strengthKevin Chiu
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09drivers/spi/spi_flash.c: Check input parameterRichard Spiegel
In procedure spi_flash_cmd_erase(), parameter "len" is not validated and could lead to the return of an invalid (non-initialized) value. Validate the parameter early on. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0b5129a15c9e0ea45f4dba4ab0729196cb64699b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device/pci_rom.c: Remove double initializationRichard Spiegel
In procedure pci_rom_probe(), variable vendev is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27949 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09arch/x86/exception.c: Remove double initializationRichard Spiegel
In procedure exception_init(), structure pointer gates is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27948 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/x86/mp_init.c: Fix error treatmentRichard Spiegel
In procedure allocate_cpu_devices(), if structure pointer new is null skip using the pointer. Add a "continue;" to skip using the pointer. The issue was found by static analysis tool. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7011fbfa0725f22a6dfbca6752e668eddac3463c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27951 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: remove disable_periodic_retraining optionsAaron Durbin
The Micron material that was broken has long since been fixed that required this option. glkrvp had these stale entries and were subsequently copied to octopus. Remove the need for this option. BUG=b:35581751 Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/intel/smm: Make sure SMRR base is aligned to SMRR sizeArthur Heymans
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09rk3288: Dig up two more KB of SRAM from under the couch cushionsJulius Werner
RK3288 has always been notoriously low on SRAM, to the point where its boards have less than 100 bytes left in both their bootblock/verstage sections. This becomes a problem every time we try to add a tiny amount of code to common coreboot interfaces that are included in them. This patch manages to add another KB to each, one from the CBMEM console (which now might get cut off a bit, but that's life) and one by moving the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write accesses must always be exactly 4 bytes long or they hang the CPU, so we mostly ignore it... but thankfully, page table entries are exactly 4 bytes long and that's the only thing we write to this region, so it works out in this case. Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-09drivers/spi/winbond: Improve structure packingPatrick Rudolph
Use bitfields to pack the struct more tightly. Change-Id: If1e7a5a3a9504327f987403ec0a7b79b2383792a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27815 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09superio: fix and extend pnp_info of wpcd376iStefan Tauner
The implementation of wpcd376i in coreboot is based on the superiotool output which apparently was incorrect. This patch refines the implementation to match the datasheet. Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-09lib/edid.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure cea_hdmi_block, the variable "b" is used as an index into a buffer of EDID bytes. At the end, it's incremented but not used, thus causing a static analysis error. Add a "(void)b;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: Ibd0b4a21bf82fcc46a627bc75564a850b7374989 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27929 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/poppy/variants/atlas: Do not override icc_maxCaveh Jalali
Skylake SoC code now sets the icc_max based on the CPU SKU, so we should not hard-code it in the device tree. BUG=b:110890675 BRANCH=None TEST=boots on atlas Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-08-08security/tpm: Report tpm_unmarshal_response warningRichard Spiegel
In procedure tpm_unmarshal_response(), variable "rc" is used early to decide if it should return NULL. Later however, the code proceeds to its end even if one subroutine reports error. If "rc" is not 0, report that there was a partial error in the procedure. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7575bc75104fd97f138224aa57561e68f6548e58 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08security/vboot: Split fwid.region build targetRaul E Rangel
Add the ability to specify the fwid version via a file instead of via config. This makes it so when doing an incremental build all objects are not invalidated when bumping the fwid. The coreboot ebuild will create this file to pass the latest version. BUG=b:112267918 TEST=ran dmidecide -t 0 and verified version was present Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-08mainboard/google/kahlee: Set SYSTEM_TYPE_LAPTOPRaul E Rangel
This configures the ACPI FADT perferred power management profile to PM_MOBILE instead of PM_DESKTOP. I'm not sure what impact this actually has. I just noticed the other boards have it set. BUG=b:110971913 TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config Change-Id: Iea1b8359b80d167e69745358f543f025713294ba Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08soc/amd/stoneyridge: Prevent reboot in romstageRaul E Rangel
By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Dump MCA registersMarshall Dawson
Add a function to provide a rudimentary dump of the Machine Check Architecture registers. These values survive a warm reset. BUG=b:65445599 TEST=Verify on a Grunt having propensity for #MC errors Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/fam15: Add MCA bank register definitionsMarshall Dawson
Define the additional registers used for each Machine Check Architecture bank. Change-Id: I962f23662789a3b974f4946555f67fcfc6147df8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Add warm reset detectionMarshall Dawson
Extend the existing reset handling features in Stoney Ridge to plan for, and recognize, warm resets. The ColdRstDet bit is always zero on a cold reset, and is intended as a mechanism for the BIOS to determine the type of a reset that occurred. Set ColdRstDet=1 after all cores have been initialized, so that any subsequent reset may be identified as warm/cold. A later patch will check the value during mp_init. Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Improve formattingMarshall Dawson
Remove for() braces from around single lines. Remove extra blank lines. This cleans up checkpatch problems in a subsequent patch. Change-Id: I329ac03365e51799581c56eed27ee54de6826f14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08ec/google/chromeec: add support for retrieving DRAM part numberAaron Durbin
The DRAM part number can be stored in the CBI data. Therefore, add support for fetching the DRAM part number from CBI. BUG=b:112203105 TEST=Fetched data from CBI on phaser during testing. Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: add new dimm info saving APIAaron Durbin
The current call for saving dimm info passed the lpddr4_cfg and memory sku id. In order to prepare decoupling the part number from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(), which explicitly takes the part number. The previous API now uses the new one internally. BUG=b:112203105 Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: Add support for LPDDR4 nWR settingRavi Sarawadi
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to be set to 24 clock cycles. The nWR field, though, is only in the GLK FSP, so just update that field conditionally based on the GLK Kconfig option. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/amd/stoneyridge/acpi.c: Remove fixed value variablesRichard Spiegel
In procedure generate_cpu_entries(), the code was copied from code that could change variables "plen" and "pcontrol_blk" based on number of cores. This is not the case with stoneyridge (2 cores only), and there's no need to use the variables. Remove them and replace with fixed values. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27877 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08device/pci_device.c: Remove unused variable attr settingRichard Spiegel
In procedure pci_get_resource, when setting an IO mapped base address, variable attr is &= with PCI_BASE_ADDRESS_IO_ATTR_MASK. However, in this particular code flow variable attr is not used later. Remove the line. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: Ia4fdda1be92d22017a7a913a911db15aaa440b69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08lib/bootmem.c: Remove unused setting of variable "begin"Richard Spiegel
The variable "begin" is extracted from the structure, but 4 lines below it's overwritten with "end - size". This causes a static build scan error that should be fixed. Remove the initial assignment of variable "begin". BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27886 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08mb/intel/cannonlake_rvp/devicetree: Remove spurious CPP directivesArthur Heymans
The devicetree is not run through a C pre-processor, so remove it. Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27927 Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08src/soc/intel/common: Configure the gspi chip select state correctlyAamir Bohra
This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/27889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07arm64: Disable MMU during legacy payload handoff (without Arm TF)Julius Werner
coreboot payloads expect to be entered with MMU disabled on arm64. The usual path via Arm TF already does this, so let's align the legacy path (without Secure Monitor) to do the same. Change-Id: I18717e00c905123d53b27a81185b534ba819c7b3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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