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2020-02-01ec/google/wilco: Set cpu id and cores to ECEric Lai
Set CPU ID and cores to EC then EC will adapt power table according to the CPU ID and number of cores. BUG=b:148126144 BRANCH=None TEST=check EC can get correct CPU id and cores. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS methodPeter Lemenkov
Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37944 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01sb/intel/common/acpi: Add more Windows versionsPeter Lemenkov
For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01mb/google/hatch: Modify kohaku's EC_SCI_EVENTS maskTim Wawrzynczak
Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=System shows ACPI interrupt as the wakeup IRQ, and the MKBP host event is properly processed as well. Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38654 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01ec/google/chromeec: Add new wrappers for host commandsTim Wawrzynczak
Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPSTim Wawrzynczak
The new host command provides these static capabilities of each USB-PD port: 1) Port number 2) Power role: source, sink, dual 3) Try-power role: none, sink, source 4) Data role: dfp, ufp, dual 5) Port location: these come from power_manager BUG=b:146506369 BRANCH=none TEST=compiles Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01mb/lenovo/t520: Switch to overridetreePeter Lemenkov
Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37295 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01nb/intel/sandybridge: improve indexed register helper macrosFelix Held
Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-01mb/google/hatch: Override CPU flex ratioSubrata Banik
This patch overrides CPU flex ratio on hatch in order to get better boot time numbers in vboot_reference. BUG=b:142264107 TEST=Able to save ~100ms of platform boot time while running with lower cpu flex ratio (i.e. freq ~1500MHz) Without this CL 1100:finished vboot kernel verification 802,443 (148,108) With this CL 1100:finished vboot kernel verification 685,382 (46,496) Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36865 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01device/pnp_device: improve warning/error messagesFelix Held
Explicitly state that the assignment is missing in the devicetree. In the case of the warnings, the missing assignments might not be an issue. Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/picasso: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/picasso: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/picasso: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/stoneyridge: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30soc/intel/common/systemagent: Add Kconfig guardAndrey Petrov
Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to some value which can't be overriden outside of soc/intel/common. So adding a non-SoC platform thats uses code from soc/intel/common is not possible. TEST=build test on wip platform Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2020-01-30src/superio/*: Fix typosPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find src/superio -name '*.[ch]') Change-Id: I36fd8cfeffdaf81d7ac646bab7ffac3e36c77879 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30mb: Fix typos in comments in AGESA boardsElyes HAOUAS
Change-Id: I4821c48ccac92f412126cea0f22cca5fd8bf8647 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-01-30mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ixEdward O'Callaghan
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again. BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix. Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30drivers/net/r8168: Add SSDT Power Resource MethodsEdward O'Callaghan
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again. V.2: Ensure reset_gpio && enable_gpio are optional. BUG=b:147026979 BRANCH=none TEST=Boot puff and do 100 cycles of S0ix. Change-Id: I3ae8dc30f45f55eec23f45e7b5fbc67a4542f87d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-30x86/acpi_device: Allow acpi_device_add_power_res params as optionalEdward O'Callaghan
Allow for making both reset_gpio && enable_gpio as optional in the params by fixing a potential NULL deref and defaulting to zero values. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I8053d7a080dfed898400c0994bcea492c826fe3d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-30arch/x86: add acpigen resource supportJonathan Zhang
Add Word/DWord/QWord Address Space Descriptor helper functions. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I707f8a443090b6f30e2940b721f9555ccdf49d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-30soc/intel/common/block/lpc: Add CMP-H LPC IDsGaggery Tsai
This patch adds CMP-H LPC IDs. TEST=Build an image and boot with discrete TPM chip. Enable measured boot and kernel could get the measured data from TPM chip. Change-Id: I7eac8b0514f79b47a05973210e2472dd1dc3d0ed Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38251 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30amd/pi/00660F01: Add missing domain_acpi_name functionJorge Fernandez
It's symmetric to the code found in 00730F01 northbridge. Change-Id: I1ee439213ff128b534f5bf130661d0ae2b9558ab Signed-off-by: Jorge Fernandez <jorgefm@cirsa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37547 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29soc/intel/skylake/acpi/dptf: Remove processor throttling controlsWim Vervoorn
The fwts method test reports errors on the methods implementing processor throttling control. The T states are not supported in coreboot at this moment. Remove the methods required by processor throttling control. They can be restored when the required support has been added to the SoC implementation. BUG=https://ticket.coreboot.org/issues/252 TEST=tested using fwts on facebook monolith. Found-by: fwts 19.12.00 Change-Id: Ib50607f60cdb2ad03e613d18b40f56a4c4a4c714 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-29amdblocks/biosram: Do small reformattingMarshall Dawson
Remove two blank lines and reorder functions by read/write sizes. Change-Id: I7bd6ed44546d49b65135a98e424a5669d90f2867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38146 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29mb/intel/kblrvp: Replace whitespaces with tabs in dsdt.aslSubrata Banik
Change-Id: I66e2cfd041f9a93668e41d79c40cec9cb1bd917e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-29soc/intel/tigerlake: Disable image clocksWonkyu Kim
TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29mb/intel/tglrvp: pin mux for image clocksWonkyu Kim
pin mux for IMGCLKOUT_0 and IMGCLKOUT_1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux for Image clocks pins(GPP_D4, GPP_H20) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifb0c2b17dd481ef6c19bdf9ee84f47ef08d7b9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-29nb/intel/i945: Use boot path macrosPaul Menzel
Change-Id: I932bd0cb97507fa159d1fe3cf2335beb31ca1caf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-28mb/hp/pavilion_m6_1035dx: Fix typosElyes HAOUAS
Change-Id: Ibd6f6bf7983382901a5327121d277606f609eca4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-28mb/lenovo: Remove unnecessary whitespace in commentsPeter Lemenkov
This makes diff between boards even smaller in some cases. Change-Id: I42ecaf5de657275708ddaf2c926fe31fe16a7220 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-28mb/intel/tglrvp: Enable DP ports for TGLRVPWonkyu Kim
TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28mainboard/supermicro/x11-lga1151-series: Disable UART3 and 4Christian Walter
With UART3 and 4 enabled, the serial console in LinuxBoot crashes. This is a short-term solution until we found and fixed the original bug. Change-Id: I75cb387ef12944232b51f6d8d41810bb27754b05 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-01-28mb/google/dedede: Add helper functions to get board_infoKarthikeyan Ramasubramanian
Add helper functions to get board's sku_id and fw_config. Enable EC_GOOGLE_CHROMEEC_BOARDID to get board_id. Add board's SKU ID and OEM name into SMBIOS table. BUG=b:144768001 TEST=Build Test. Change-Id: Id1729e245accf5acc29307a22721362fb1ce0878 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38551 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28mb/google/fizz/variants/endeavour: Enable root ports for TPUsJeff Chase
BUG=b:148221635 TEST=build;install;lspci Change-Id: I1732f7fe64ace41a721a2d6a964988efc97b2579 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38550 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-28commonlib: Add commonlib/bsdJulius Werner
This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed <commonlib/helpers.h> as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing <commonlib/compression.h> (written by me) and <commonlib/compiler.h> (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from <types.h> into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-27nb/intel/sandybridge/raminit_common.h: add missing stdint.h includeFelix Held
Types from stdint.h are used in that header file without stdint.h being included. Change-Id: I71449dd26162dc8420c206285896ac9a8e4e04d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-27nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE defineFelix Held
The two defines are identical, so deduplicate this. Timeless build for lenovo/x230 results in identical binary. Change-Id: I32e0eee88d72eb6f8dc71b0324d62f46079120a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-27google/octopus: Disable bootblock consoleJulius Werner
The GLK bootblock seems(?) to be hard limited to 32KB and some Octopus variants are so close to that that they only have 0.5KB left. This is blocking development of new core features, so let's disable the bootblock console to gain a couple of KB back (like we already did on RK3288). There are probably other opporunities for code size reduction here (e.g. it seems that almost half(!) of that whole bootblock size is taken up by devicetree.cb structures), but I'm not familiar enough with the platform to dig into them. Change-Id: I05b4ecf5abef7307e3d0a81db04a745ff3da0c42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38521 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-27mb/gigabyte/ga-b75m-d3h: add ACPI definitions for legacy PCI slotsBill XIE
All variants of ga-b75m-d3h lack ACPI definitions for legacy PCI slots, which causes IRQ issue if it gets legacy PCI card installed. The missing definitions (mainly Interrupt Routing Table) are added to fix that. NOTE: The added definitions are actually for ga-b75-d3v, but since they form superset of definitions needed by ga-b75m-d3{h,v}, they can be applied to all three existing variants with suitable preprocessor instructions. Change-Id: Id79c759a5fadb38c2873edc07293cbb14401ac9a Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-27mainboard/google/hatch: Set GPP_C7 as the wake pin for the NIC on PuffSam McNally
BUG=b:148252157 BRANCH=none TEST=Put a puff in s0ix, send a WoL magic packet. Change-Id: I4a08a2f5505d00909c9301315fcf72f687141f91 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-27ec/google/wilco: add ec command set cpu idEric Lai
Add new mailbox command support. Set CPU ID and cores to EC. EC will according to different CPU to set different power table. BUG=b:148126144 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I135d2421d2106934be996a1780786f6bb0bf6b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-01-27mainboard/system76: Add System76 Lemur Pro (lemp9)Jeremy Soller
The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support in coreboot is developed by System76 and provided as the default firmware option. Testing is done on a pre-production model expected to be identical from a firmware perspective to the production model. Working: - Payload - Tianocore - CPU - Intel i7-10510U - Intel i5-10210U - EC - ITE IT5570E running https://github.com/system76/ec - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys - Battery - Charger, using AC adapter or USB-C PD - Suspend/resume - Touchpad - GPU - Intel UHD Graphics 620 - GOP driver is recommended, VBT is provided - eDP 14-inch 1920x1080 LCD - HDMI video - USB-C DisplayPort video - Memory - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM - Networking - M.2 PCIe/CNVi WiFi/Bluetooth - Sound - Realtek ALC293D - Internal speaker - Internal microphone - Combined headphone/microphone 3.5-mm jack - HDMI audio - USB-C DisplayPort audio - Storage - M.2 PCIe/SATA SSD-1 - M.2 PCIe/SATA SSD-2 - RTS5227S MicroSD card reader - USB - 1280x720 CCD camera - USB 3.1 Gen 2 Type-C (left) - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) Not working: - TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0 are not currently supported by the intel fast_spi driver. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-27mb/intel/tglrvp: Enable MIPI cameraWonkyu Kim
Add MIPI camera ACPI Update GPIO pin mux for camera BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check camera Simple test method to check camera: capture image by below commands from OS console >media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]" >media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]" >yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10 $(media-ctl -e "Intel IPU6 CSI2 BE capture") Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4189e96f68f0e64e0860405e00eeab84564b86be Reviewed-on: https://review.coreboot.org/c/coreboot/+/37863 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-27src/Kconfig: Remove unused symbolElyes HAOUAS
The use of ENABLE_APIC_EXT_ID removed with commit: de56a66e Change-Id: I24c07c9a4813ceba48082ca2c564266435e58a18 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38575 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 07:16:08 +0000