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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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2018-11-13
mb/cannonlake: Remove SmbusEnable from devicetree
Duncan Laurie
2018-11-13
soc/intel/icelake: Update GPIOs for Icelake SOC
Aamir Bohra
2018-11-13
mb/opencellular/rotundu: Remove unused CACHE_ROM_SIZE_OVERRIDE
Elyes HAOUAS
2018-11-13
soc/intel/common: Add option to call EC _PTS/_WAK methods
Duncan Laurie
2018-11-12
mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggered
Furquan Shaikh
2018-11-12
mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK
Patrick Rudolph
2018-11-12
mb/emulation/qemu-i440fx|q35: Get rid of unused headers
Patrick Rudolph
2018-11-12
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
Arthur Heymans
2018-11-12
intel/i945: Factor out ram init time stamps
Paul Menzel
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-11-12
mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"
Elyes HAOUAS
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-12
mb/google/octopus/variants/fleex: Set up tcc offset for fleex
John Su
2018-11-12
ec/google/chromeec: Configure EC_SYNC_IRQ as level triggered
Furquan Shaikh
2018-11-11
mb/emulation/qemu-i440fx|q35: Link memory.c
Patrick Rudolph
2018-11-10
mb/lenovo/t400: Improve docking code
Patrick Rudolph
2018-11-09
soc/intel/apollolake: Disable HECI1 before jumping to OS
Furquan Shaikh
2018-11-09
arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATION
Furquan Shaikh
2018-11-09
drivers/*/tpm: Add postcar target
Philipp Deppenwiese
2018-11-09
include/program_loading: Add POSTCAR prog type
Philipp Deppenwiese
2018-11-09
intel/i945: add timestamps in romstage
Patrick Georgi
2018-11-09
mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 ms
Chris Wang
2018-11-09
mb/google/kahlee: Tune eDP panel initialization time
Chris Wang
2018-11-09
mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ge...
Subrata Banik
2018-11-08
mb/google/sarien: Set runtime IRQs to reset on PLTRST
Duncan Laurie
2018-11-08
mb/google/sarien: Disable eSPI when ACPI is enabled
Duncan Laurie
2018-11-08
soc/intel/common: Add option to disable eSPI SMI at runtime
Duncan Laurie
2018-11-08
mediatek/mt8183: Add DDR driver of write leveling part
Huayang Duan
2018-11-08
mediatek/mt8183: Add DDR driver of cmd bus training part
Huayang Duan
2018-11-08
mediatek/mt8183: Add DDR driver of pre-calibration part
Huayang Duan
2018-11-08
security/vboot: Add selection for firmware slots used by VBOOT
Philipp Deppenwiese
2018-11-08
nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros
Elyes HAOUAS
2018-11-08
src: Replace common MSR addresses with macros
Elyes HAOUAS
2018-11-08
nb/intel/gm45: Use macro instead of magic number
Elyes HAOUAS
2018-11-08
soc/intel/skylake: Add PCH sku id's supported for KBL
Praveen hodagatta pranesh
2018-11-08
mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST
Nick Vaccaro
2018-11-08
mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
Nick Vaccaro
2018-11-08
mb/google/octopus/variants/baseboard: Improve cold boot and S3 resume
John Zhao
2018-11-08
soc/intel/apollolake: Improve cold boot and S3 resume
John Zhao
2018-11-08
mb/google/poppy/variants/nami: add the hynix memory parts
Ren Kuo
2018-11-08
src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2
Michał Żygowski
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