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2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-18lynxpoint: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Ie8e4fffcec308d1cd5e696605e78671f3ababf40 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18via/vt8454c: Migrate to per-device ACPIVladimir Serbinenko
Change-Id: Ia3f6691ae7c33b5e22010e25a1f01996a594196e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6943 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18i3100: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18via/vx800: Migrate to collaborative ACPIVladimir Serbinenko
Change-Id: I00d0d0e2556d4cd0553a2b3351ace26bf747ff6a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6944 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18fsp_sandybridge: Move to per-device ACPI.Vladimir Serbinenko
Just took combined sandybridge per-device ACPI patch and applied it on FSP flavour to avoid need of separate tests. Change-Id: I09838cc01ede504416078edcb1c267a11539e714 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18sch: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18cimx/sb800: fix pedantic gcc errorRonald G. Minnich
A cast did not work for me, but this variable did. This is one of the many issues with building e3501 I'm running into. Change-Id: Ifb19a17770604f2d63dfef762d08200add77ee34 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7122 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18intel/i82801bx: Minor log fixes in IDE driverPatrick Georgi
Two issues: 1. without config, there were two NULL derefs 2. output for "Secondary" looked at ide0_enable Change-Id: I34ddbc0f9b27226981ccbc237e3d59e522076d55 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18various AMD boards: fix buffer overflowPatrick Georgi
"AMD\t " isn't 8 characters long. Change-Id: I47b2a39d7dca0201b7ee5dfd1f77e0714411257c Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6991 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-10-18e7505: Move to per-device ACPIVladimir Serbinenko
Change-Id: I706891b9408cf14b559ef228766c04e98345ff6e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18i945: Consolidate FADT codeVladimir Serbinenko
Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7087 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17lenovo/t520: Use native raminit over MRC blobNicolas Reinecke
Native raminit for sandy/ivybridge was introduced in: 7686a56 sandy/ivybridge: Native raminit. An additional current level is needed. Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7098 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-10-17boot/coreboot_tables.h: Use `it is` instead of `it easy` in commentPaul Menzel
Change-Id: I5c8a689a4923175fff1f38847b7cfbbaeeb0ea22 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7092 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17lenovo/t520: Enable wake on LID and Fn keyNicolas Reinecke
Change-Id: Ieb23728ba171733820830e86e77a4c6d8e1cc57d Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7101 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/t520: Apply ME workaround for S3 resumeNicolas Reinecke
Without this patch the laptop powers down after resume. Change-Id: Ic6486fd4c4cc55b1ac5695f9d6d83fc2193b7eba Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7102 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/t520: fix board infoNicolas Reinecke
Change-Id: Ieeefbe4617ea6c131236d8c94e9990f7b797192b Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7103 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17asus/m5a88-v: Fix southbridge initKyösti Mälkki
This amdfam10 board was by mistake modified with commit b6f3da4 AGESA CIMx: Move late init out of get_bus_conf() Change-Id: I8edf6f7f4cc635d31e7e485e3f6de57ef8ed7b1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-17lenovo/t520: Use native LVDS gfx initNicolas Reinecke
As introduced in: 1783a3c ivybridge: LVDS gfx init. The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table. Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7100 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/T520: Remove butterfly DSP init.Nicolas Reinecke
It's specific to butterfly. Doesn't do anything on lenovos. Change-Id: I98b7c3199de5d8515bd869936e1b95847321d264 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Fix ICH spi implementation which reads data from different chips.Philipp Deppenwiese
This patch adjusts the read timeout in order to support flash chips which needs more than 60ms to complete a spi command. This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ). Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17macbook21: Kill empty gpe.aslVladimir Serbinenko
Change-Id: I4ed04ecbc9e11200577cc2b6ede0e05af9f346fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7082 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-10-17macbook21: Kill empty Makefile.incVladimir Serbinenko
Change-Id: I2d946b9d757cc6158ff7f8927a81d7bf03a2e062 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7084 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Kconfig: move SMBIOS related options to SMBIOS table optionStefan Reinauer
Change-Id: I74943d0248f49796b9d31d6ed827c69f8cea13a5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17macbook21: Kill empty smi.hVladimir Serbinenko
Change-Id: I387bb6154fe432ef2fc5f92faca69e67d7a6370a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7083 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Kconfig: clean up options in top level and device menuStefan Reinauer
Move generic options to the "General Setup" menu. Move device specific options to the "Devices" menu. Change-Id: I514a021305d43f026b24fd3016477300700ed401 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17bd82x6x: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17macbook21: Kill empty mainboard.aslVladimir Serbinenko
Change-Id: I29c7d367df7d1ce911f6cd7ed5e5c56865b41dcc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7063 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17drivers/spi: Add support for Micron N25Q128Scott Radcliffe
Support added for Micron N25Q128 SPI flash, which has the same manufacturer id as ST Micro. Jedec ID = 0x20 0xBB 0x18. Since existing stmicro.c only compares the last device id byte, this flash is mistakenly identified as M25P128, which has ID = 0x20 0x20 0x18. To handle this situation and avoid breaking code for existing devices, a two byte .id member is added. New devices should be added to the beginning of the flash table array with .idcode = STM_ID_USE_ALT_ID and .id = the two byte jedec device id. A 4KB subsector erase capability is added and used for this new device. It requires using a different SPI op-code supported by adding .op_erase member. Previous devices defined in stmicro.c are assigned their original op-code for 64KB sector erase. N25Q128 is now working on a custom designed Bayley Bay based board. Tested by verifying the MRC fastboot cache is successfully (re)written. Note that previous devices were not retested. Change-Id: Ic63d86958bf8d301898a157b435f549a0dd9893c Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7077 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-10-17bd82x6x: Consolidate early native USB initVladimir Serbinenko
Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17acpi_add_ssdt_pstates: Remove function.Vladimir Serbinenko
Nowhere in database p_state_num is set. So this whole function ends up being a noop. Moreover the offsets used by it are wrong with any optimizing iasl. Remove it in preparation of move to per-device ACPI. Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17xe7501devkit: Kill unused cmos.layoutVladimir Serbinenko
Change-Id: I04b485945a1830deaf5a695507ea81809edbceeb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7073 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Fix mismerge of ACPI patchesVladimir Serbinenko
Change-Id: I2a9960861465f4686113213d5e5793333b6274b2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7079 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16smbios: Mark laptops as suchVladimir Serbinenko
Change-Id: I179a4cede2f826f72a400208748798737216c01a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7071 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-10-16uarts: 32/64 cleanupRonald G. Minnich
We had lots of casts that caused warnings when compiling on RISCV. Clean them up. Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7066 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16lib/cbfs: more cleanup for 32/64 issuesRonald G. Minnich
Change-Id: I5499a99cec82b464c5146cfc2008d683d079b23a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7068 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16cbmem: 64/32 cleanupRonald G. Minnich
Change-Id: I4b55b635cc233a9d48b284623399277d941b0d5a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7069 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-16qemu-armv7: 32/64Ronald G. Minnich
This really is not critical but we might as well get it right. Change-Id: Ifec1e8dc35d7f5bb89d9a7a877d82410c83a3288 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7070 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-16x220, x230: Remove unused headers.Vladimir Serbinenko
Change-Id: Ia85e3b588c0e255e5c0f77114f051130596ce8d5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6922 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.Vladimir Serbinenko
Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16sandybridge: Move common northbridge finalize to northbridge code.Vladimir Serbinenko
Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6920 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16lenovo/{x2,t5}{2,3}0: Remove butterfly DSP init.Vladimir Serbinenko
It's specific to butterfly. Doesn't do anything on lenovos. Change-Id: I7b607196733225eace0f5e70b4cc02651488aa74 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-16amdk8: Move to per-device ACPIVladimir Serbinenko
Change-Id: I485791015aa7eaabba53813945c216f5725554b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-15i945: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-15gm45: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7039 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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