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2018-02-02ec/google/chromeec: Remove wake flag from keyboard IRQDuncan Laurie
The keyboard IRQ was changed to ExclusiveAndWake in order to support waking from suspend-to-idle (S0ix) with commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0 http://review.coreboot.org/11712 However this is triggering a kernel panic on Windows 10 because it apparently does not like legacy device interrupts to to be set as wake capable. This change is no longer necessary because the linux kernel was changed to always treat the keyboard as wake capable: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/input/serio/i8042.c?id=f13b2065de8147a1652b830ea5db961cf80c09df Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23563 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02mb/google/kahlee/mainboard.c: Create mainboard_pirq_dataRichard Spiegel
When booting kahlee, there's an error message: "Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist". This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data. BUG=b:70788755 TEST=Build and boot kahlee. Warning message must be gone. Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-02nb/intel/sandybridge: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I6dfef118dc2fecf2a8f2f3401c779a3becfb71a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-02arch/x86/acpi/statdef.asl: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I8c49853a54fc301d39dc7c362f2085c25fad7fbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-02drivers/i2c/designware: conform to controller restrictionsAaron Durbin
The designware i2c controller indicates that the slave address shouldn't be programmed while the controller is enabled. Therefore, switch the ordering of the slave target address and the enable. Additionally, ensure the controller is disabled prior to the start of the slave programming sequence. Lastly, chunk up the i2c_msg segments at differing slave address boundaries. That allows for simpler programming for the controller by only doing one slave address transaction chunk at a time. BUG=b:70232394,b:69250772 Change-Id: Iebc08e2db847cb182fad98e0ff3d799b9a64aca7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01Add a default path for vbt.binArthur Heymans
FSP_GOP needs a vbt.bin to work but before this patch it was able to build with the default configuration which was an empty path for vbt.bin. To make Jenkins happy don't select FSP_GOP by default, at least until all boards have the proper vbt blobs in the blobs repo. Change-Id: Ibc36d6d4dd1a56c53819b169e6f4799ce3c23e03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-01vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9Marc Jones
Update the shared AGESA headers to 1.3.0.9. This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated to the same version. BUG=b:72679320 TEST=build and boot Grunt Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01lib/stage_cache: Add debug messages for failuresMarshall Dawson
Communicate additional status to the console when the save and load functions do not function as expected. The most likely scenario for an error is when using a cache that is external to cbmem, and restricted in size. Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01amd/soc/common: Remove cbmem subregions in heapMarshall Dawson
Revert most of 4f3f47b "amd/common: Define regions in cbmem". This puts the management of the heap space back to its traditional methodology. Subsequent patches that were to have used these subregions have been reworked. BUG=b:69614064 Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01drivers/i2c/designware: Unset IC_ENABLE when setting target addressChris Ching
To set address on AMD, IC_ENABLE == 0. BUG=b:69416132 BRANCH=none TEST=Test communication with i2c TPM on grunt and coral Change-Id: I7faee8e11439deceab946cc82d30d274b529b90d Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/23293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-01mb/google/kahlee: always load and run display opromAaron Durbin
The kernel requires the display oprom is loaded *and* ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:72400950 Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23506 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01device: add ALWAYS_RUN_OPROM optionAaron Durbin
Certain platforms require that the option rom always needs to be ran in order for display to work correctly. Therefore, provide this ability for the platform to select such that we force option rom loading. BUG=b:72400950 Change-Id: I597bc8af7ac8b68fe8505aac5f1c7e1ccd34ac27 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23505 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01device/pci_device: remove #if/#endif in oprom logicAaron Durbin
Use C if conditions instead of preprocessor macros. BUG=b:72400950 Change-Id: I8107f94b9ecb6f32c569cad0bcb3d51ab39aa35c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23504 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31amd/stoneyridge: Move TValid and SmmLock to end of POSTMarshall Dawson
Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-31commonlib: Add AGESA S3 resume definesMarshall Dawson
Extend the values reserved for AGESA to include the Entry Points used for S3 Resume. BUG=b:69614064 Change-Id: I6b50e76a0c49c1f317f9294c5f95735e7aa5d95c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31mb/google/kahlee: Add grunt cr50 supportJustin TerAvest
This commit adds an entry for H1/Cr50 into the devicetree for setting up ACPI entries for H1 communication. BUG=b:69250772 TEST=See probe messages in dmesg Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23514 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31mb/google/kahlee: Add grunt trackpad in devicetreeJustin TerAvest
This commit removes a manually written asl file in favor of configuring the trackpad through devicetree. BUG=b:72121803 TEST=cat /proc/interrupts with trackpad connected Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23508 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-31nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph
The code has been moved into drivers folder. Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-31soc/intel/skylake: Always add PM1_TMR block to FADTDuncan Laurie
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-31soc/intel/skylake: Fix common timer frequencyDuncan Laurie
The calculation to set up the PM timer emulation is using an incorrect common timer clock value that was copied from Apollolake. According to the PDG Skylake and Kabylake clocks are derived from a 24MHz XTAL, not 19.2MHz like Apollolake. Fixing this value results in the proper "correction value" to be programmed into the PM timer emulation MSR that matches the raw value that would be programmed by FSP. (if it were doing MpInit) Old PM timer correction value: 0x2fba2e25 New PM timer correction value: 0x262e8b51 Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23509 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31device/pci_rom: Write _ROM method for VGA devicesPatrick Rudolph
Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31arch/x86/acpigen: Add generator for _ROMPatrick Rudolph
Generate ACPI AML code for _ROM method. This function takes as input ROM data and ROM length. Arguments passed into _DSM method: Arg0 = Offset in Bytes Arg1 = Bytes to return Example: acpigen_write_rom(0xdeadbeef, 0x10000) AML code generated would look like: Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory { OperationRegion (ROMS, SystemMemory, 0xdeadbeef, 0x00010000) Field (ROMS, AnyAcc, NoLock, Preserve) { Offset (0x00), RBF0, 524288 } Local0 = Arg0 Local1 = Arg1 If (Local1 > 0x1000) { Local1 = 0x1000 } If (Local0 > 0x00010000) { Return (Buffer (Local1) { 0x00 }) } If (Local0 > 0x0f000) { Local2 = 0x10000 - Local0 If (Local1 > Local2) { Local1 = Local2 } } Name (ROM1, Buffer (Local1) { 0x00 }) Local1 *= 0x08 Local0 *= 0x08 CreateField (RBF0, Local0, Local1, TMPB) ROM1 = TMPB /* \_SB_.PCI0.GFX0._ROM.TMPB */ Return (ROM1) /* \_SB_.PCI0.GFX0._ROM.ROM1 */ } Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-31soc/intel/cannonlake: CannonaLake make use of FVI informationSubrata Banik
Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required firmware information right after FSP-S. TEST=Display FW information as below >> Display FSP Version Info HOB Reference Code - CPU = 7.1.20.52 uCode Version = 0.0.0.16 Reference Code - ME 11.0 = 7.1.20.52 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - CNL PCH = 7.1.20.52 PCH-CRID Status = Disabled CNL PCH H A0 Hsio Version = 2.0.0.0 CNL PCH H Ax Hsio Version = 9.0.0.0 CNL PCH H Bx Hsio Version = 5.0.0.0 CNL PCH LP Ax Hsio Version = 13.0.0.0 CNL PCH LP B0 Hsio Version = 7.0.0.0 CNL PCH LP Bx Hsio Version = 6.0.0.0 CNL PCH LP Dx Hsio Version = 2.0.0.0 Reference Code - SA - System Agent = 7.1.20.52 Reference Code - MRC = 0.5.1.19 SA - PCIe Version = 7.1.20.52 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.0 SA-CRID New Value = 0.0.0.0 Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23387 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Add support to display FSP version info HobSubrata Banik
This patch locates FSP FVI hob in order to extract all firmware ingredient version information. So far this feature is only supported for CannonLake SoC onwards. Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob headerSubrata Banik
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot platform using CannonLake FSP new feature. Expectation is that, FSP will provide version information of all Firmware ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code, CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version, PCH Ref Code version etc.) Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.20.52. Following changes had been made: 1. Hide internal EV related options. 2. Add GT voltage override options. 3. Add PEG IMR selection. 4. Add PCH DMI ASPM options. TEST=NONE Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31vendorcode/intel/fsp: Remove TODOs and make use of EDK2 headerSubrata Banik
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Make use of Resource Type macro from EDK codeSubrata Banik
Users are getting build error due to duplicate macro definitions of same resource type between fsp driver code and UEFI headers. Hence this patch ensures to refer a single source location for macro definitions to avoid compilation error. Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add Kconfig option to get UDK_VERSIONSubrata Banik
This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31vendorcode/intel: Add UDK2017 supportSubrata Banik
This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31mb/google/poppy/variants/nautilus: Add gpio-keys ACPI node for PENHFurquan Shaikh
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:71329519 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: Ib293c2ca532c8ed9e2587143b1a69300cd9fa4e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-31drivers/gpio_keys: Add driver for handling gpio-keysFurquan Shaikh
This change adds the required device node in SSDT for defining gpio-keys/gpio-keys-polled. Currently, it supports only one gpio-key per device node. BUG=b:71329519 TEST=Verified by adding details to devicetree that device node is added to SSDT: Device (PENH) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionInputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x002B } }) Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "compatible", "gpio-keys" } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { Package (0x02) { "button-0", "EJCT" } } }) Name (EJCT, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x04) { Package (0x02) { "linux,code", 0x0F }, Package (0x02) { "linux,input-type", 0x05 }, Package (0x02) { "label", "pen_eject" }, Package (0x02) { "gpios", Package (0x04) { \_SB.PCI0.I2C0.PENH, Zero, Zero, One } } } }) } Change-Id: I6f11397b17d9de1c87d56f6a61669ef4052ec27b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23236 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30mainboard/google/zoombini/variant/meowth: enable FCAM_PWR_ENNick Vaccaro
Turn on power for front camera at startup in coreboot (needs to be set for factory scan). BUG=b:69011806 BRANCH=master TEST=none Change-Id: I2f31b19dfef5fe386b485dd675f0ff981288acf4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variant/meowth: fix SPD issuesNick Vaccaro
Fix incorrect settings in the Hynix 4GB and Samsung 2GB SPD files for meowth. BUG=b:69011806 BRANCH=none TEST=Confirm meowth with Hynix 16GB and meowth with Samsung 8GB solutions boot. Change-Id: Ia2ac564541b57647c3b605ce3389d74251490ca0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23388 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mainboard/google/zoombini/variants/meowth: enable I2C bus #2Nick Vaccaro
Enable I2C #2 for display backlight controller. BUG=b:69011806 BRANCH=none TEST=none Change-Id: I5440bd4265414c55458a73e293a9931145a158cc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-30mainboard/google/zoombini/variants/meowth: Add rev 2 gpio changesNick Vaccaro
Change GPIO settings for meowth rev 2 boards. Changes include: - GPP_B7 set to no-connect - GPP_C1 set to no-connect - GPP_D8 set to no-connect - GPP_D9 (PP3300_WLAN_EN) set as output with initial value high - GPP_E9 (DCI_CLK) set to no-connect - GPP_E10 (DCI_DATA) set to no-connect BUG=b:72202352 BRANCH=none TEST=none Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variants/meowth: Fix USB OC settingsNick Vaccaro
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings were causing false overcurrent conditions as OC0 and OC1 were used for other purposes. Remove initialization of unused usb3 ports, and configure the ports we use (usb3 ports 0 & 1) to use OC2 and OC3, respectively. BUG=b:72250084 BRANCH=none TEST=Verify meowth can recognize and boot off a kernel on USB drive. Change-Id: I528b67d80a1da84e5307facb40de545089979f57 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mb/google/poppy/variants/soraka: Update _PSV for TCPUFurquan Shaikh
This change updates the passive setting for TCPU as per factory team recommendation. BUG=b:65467566 Change-Id: I081f63bdf811ff021c398f60efec9e6cccf462d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23494 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30mb/google/poppy/variants/soraka: Enable mode-aware DPTFFurquan Shaikh
This change selects EC tablet event and provides trip point temperatures for tablet and non-tablet mode so that DPTF can be supported depending upon device mode. BUG=b:65467566 TEST=Verified by changing modes that the trip point temperatures are updated in the OS (/sys/devices/virtual/thermal/thermal_zone{2,3,4,5}). Change-Id: I071868982fa87821550b870a6d8050cf2a030b49 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23463 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30soc/intel/skylake: Add support for mode-aware DPTFFurquan Shaikh
This change adds support for: 1. Handling thermal trip points change event handler based on device mode. 2. Returning thermal trip point temperatures based on the device mode. BUG=b:72554519 Change-Id: Ife48af76ceb7a39abd1fac8ef1f77db7e65ab43e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30drivers/i2c/tpm: Add irq_gpio support to tpm.Justin TerAvest
Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with the tpm. This change allows devicetree entries to use a irq_gpio entry to describe the interface with the TPM. BUG=b:72655090 Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mb/google/kahlee: correct comments in baseboard gpio.cAaron Durbin
The gpios for 147 and 148 are connected to PCH_I2C_HUB_SCL and PCH_I2C_H1_TPM_SDA, respectively. Fix the comment. BUG=b:64140392 Change-Id: Ibebf6ce7d9fb26276b12b9c9844c260413f0337e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30mb/google/kahlee: mark h1 bus as early init for gruntAaron Durbin
Since the h1 i2c bus is required for verstage mark the bus as needing to be initialized early. That way, the bus is initialized in bootblock prior to verstage. BUG=b:70232394,b:69250772 Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30soc/amd/stoneyridge: initialize i2c buses marked as early initAaron Durbin
Initialize the i2c buses that are marked as early init in the device tree. BUG=b:70232394,b:69250772 Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30soc/amd/stoneyridge: fix gpio_acpi_path()Aaron Durbin
The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix the path so that it references the system bus. BUG=b:72121803 Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23501 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: use new host controller programmingAaron Durbin
The SPI controller on stoneyridge apparently has a large fifo and an alternate method for programming the controller. The fifo is directly accessible as well as the rx and tx pointer in addition to the execute bit. Remove the unneeded #defines and program the host controller with the above changes in mind. In addition, add debug hooks to the driver so one can dump the state of the controller when in operation. The time it took to read 4KiB of flash in the elog driver went from 20593 microseconds to 5693 microseconds on cdx03/kahlee. BUG=b:65485690 Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23493 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: utilize full SPI flash controller fifoAaron Durbin
The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30drivers/spi: support cmd opcode deduction for spi_crop_chunk()Aaron Durbin
spi_crop_chunk() currently supports deducting the command length when determining maximum payload size in a transaction. Add support for deducting just the opcode part of the command by replacing deduct_cmd_len field to generic flags field. The two enums supported drive the logic within spi_crop_chunk(): SPI_CNTRLR_DEDUCT_CMD_LEN SPI_CNTRLR_DEDUCT_OPCODE_LEN All existing users of deduct_cmd_len were converted to using the flags field. BUG=b:65485690 Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23491 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 04:52:20 +0000