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2011-10-20i82801dx: Replace romstage printk'sKyösti Mälkki
Patch is required to compile this with romcc. Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/291 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19asrock/e350m1: Enable the superio ACPI device in devicetree.cbPeter Stuge
This makes the power_on_after_fail NVRAM option work correctly. Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/292 Tested-by: build bot (Jenkins)
2011-10-19IOAPIC: fix bitmaskKyösti Mälkki
APIC ID is bits 27..24, not 19..16. Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/299 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19sconfig: check whether component directory actually existsStefan Reinauer
and add drivers/generic/generic back (empty), since it is used by many devicetree.cb files. Without this patch typos in component names in devicetree.cb cause the component to be silently ignored. Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/270 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19Drop eh_frame instead of moving it into the image.Stefan Reinauer
That's what SeaBIOS does, too, and it works just fine. Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/269 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19I945: replace #if defined() by #ifSven Schnelle
config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/293 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18Append logical PME/GPIO device. Fix MPU device number.Kyösti Mälkki
A mainboard may require configuration of the superio pins to fully support some features. Things like A20# gate, leds, fans, infra-red and bootstrap jumpers may be configured and controlled through the logical PME device. Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/289 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
As new microcode files were included, the table was not updated with families 0f25 and 0f26. Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-17Fix our CMOS checksum algorithm so it matches what /dev/nvram expectsStefan Reinauer
Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it! Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1 Signed-off-by: Vadim Bendebury <vbendeb@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/279 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17rework RTC driver output to make it more consistent.Stefan Reinauer
Also add a meaningful define (Not hooked up in Kconfig, that might or might not follow) Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/278 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17Re-worked devicetree.cb for DL145 G1Oskar Enoksson
After a lot of experimentation this commit improves some hardware features that were not recognized or incorrectly configured before. The only thing not tested is SCSI-option board (I dont have one). Misleading errors in comments have been corrected. (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade which was supported in early versions of coreboot but was dropped for some reason.) Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e Reviewed-on: http://review.coreboot.org/237 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
First issue fixed: For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug by really emitting one Processor object for each core. However, the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Fourth issue: If a processor without PowerNow! support was inserted in a system with coreboot configured with SET_FIDVID then the boot process hanged mysteriously and very early. Apparently because init_fidvid_ap tampers with non-existing registers. This commit fixes the bug by bailing out from init_fidvid_ap if PowerNow! capability is missing. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 Reviewed-on: http://review.coreboot.org/239 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
According to Rudolf Marek putting a memory instruction between the CR0 write and the jmp in protected mode switching might hang the machine. Move it after the jmp. There might be a better solution for this, such as enabling the cache, as keeping it disabled does not prevent cache poisoning attacks, so there is no real point. However, Intel docs say that SMM code in ASEG is always running uncached, so we might want to consider running SMM out of TSEG instead, as well. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec Reviewed-on: http://review.coreboot.org/283 Reviewed-by: Sven Schnelle <svens@stackframe.org> Tested-by: build bot (Jenkins)
2011-10-15use byteorder.h instead of implementing another byte swap functionStefan Reinauer
Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15cbfs_and_run_core() is not part of the API, make it static.Stefan Reinauer
It's only used in cbfs_and_run.c Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/273 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-10-15reformat Makefile.bootblock.inc (>80 lines per char)Stefan Reinauer
Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/274 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6Stefan Reinauer
Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/268 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of AMD GX2 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/267 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of VIA CN700 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14fix compilation of intel/sch northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6Stefan Reinauer
Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13Prevent build breakage without consoles enabledStefan Reinauer
If all console types are disabled, coreboot will fail to compile because static code is unused. This patch fixes the issue. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2 Reviewed-on: http://review.coreboot.org/260 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Load an IDT with NULL limitStefan Reinauer
Load an IDT with NULL limit to prevent the 16bit IDT being used in protected mode before c_start.S sets up a 32bit IDT when entering ram stage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e Reviewed-on: http://review.coreboot.org/259 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix compilation of x86emu with gcc 4.6.xStefan Reinauer
gcc 4.6 complains about unused but set variables in x86emu. Particularly some variables are always set but only used in debug mode, or when FPU support is enabled. Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/258 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix native x86 option rom initializationStefan Reinauer
- Intel option roms want an initialized i8259 or they will throw an exception 6. This should be done in the southbridge code, but that is executed much later than the VGA init, so initialize the i8259 in src/devices/oprom/x86.c. In the long run this will allow getting rid of some of the ugly hacks in some AMD boards' romstage.c - Don't overwrite the mode when copying mode info information back from 0x600. Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/257 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13refactor vesa mode setting code and bootsplash codeStefan Reinauer
- adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/256 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Refactor option rom initialization code in coreboot.Stefan Reinauer
- move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/255 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Enable/fix compilation of i8254 code in ram stage.Stefan Reinauer
Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/254 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix romstage creation with gcc 4.6 and CAR targetsStefan Reinauer
newer gcc versions generate ".section .text" instead of just ".text" in their assembler output. This patch makes sure that we don't end up with a superfluous ".section" that makes the build fail. Add -Wno-unused-but-set-variable to CFLAGS if the flag exists. Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/252 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13siemens/sitemp_g1p1: Don't mess with virtual wire settingsPatrick Georgi
That function broke SMP on Linux 2.4, now it works. Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/243 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13siemens/sitemp_g1p1: Get rid of bus_isa and bus_typePatrick Georgi
Each variable is essentially unused or incorrect. Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/242 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13amd/sb600: Enable COM2 at all times in early setupPatrick Georgi
Otherwise with a coreboot log on COM2 (which doesn't work) the boot process takes eons. Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/241 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Make Asus A8V-E SE better ACPI citizen.Rudolf Marek
Use the SSDT autogen infrastructure to support the automatic reserved resources, automatic P-state generation and automatic _CRS PCI0 method. Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-12w83627hf: ASL include containing virtual device tree of the SuperIOChristoph Grenz
Add a ACPI Source Language snippet to superio/w83627hf which maps the SuperIO and most of the logical devices to PnP devices, exposing configuration options and chip power management to the OS. Written using the Winbond W83627HF/F datasheet. Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/223 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12amdk8: ASL include for K8 temperature sensor support in ACPIChristoph Grenz
Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/222 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12SB800 RAID: add kconfig option RAID_MISC_ROM_POSITIONKerry Sheh
SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12SB800: Sata Enable bus master and enable ahci for AHCI/RAID modeKerry Sheh
In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12avalue/eax-785e: Get SATA Mode from Kconfig optionKerry Sheh
Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/233 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODEKerry Sheh
Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/231 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12persimmon: complete the sb800 devicetreeKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. So the missing sb800 USB3 devicees was add to the mainboard devicetree. Because of no physical usb connector connected to USB3, the USB3 device setting was off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/232 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson
AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to mark dram memory above 4GB as WB. However, AMD K8 rev E and earlier don't implement this bit and therefore need MTRR spanning dram memory above 4GB. The current implementation of amd_setup_mtrrs never generate MTRR above 4GB. This caused memory > 4GB not to be recognized in e.g. Linux on those rev E or older platforms. This commit should fix that bug. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1 Reviewed-on: http://review.coreboot.org/238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11mainboard: complete the sb800 devicetree even device is offKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/230 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11sb800: sata combine mode configure fixKerry Sheh
Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/229 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11persimmon: sb800 sata mode configure updateKerry Sheh
persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/227 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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