summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2017-05-18uart: Fix bug in {uart8250, uart8250_mem, ns16550}_rx_byte functionsWerner Zeh
We have several different UART implementations of which three support a timeout when receiving characters. In all of these three implementations there is a bug where when the timeout is hit the last received character will be returned instead of the needed 0. The problem is that the timeout variable i is decremented after it has been checked in the while-loop. That leads to the fact that when the while-loop is aborted due to a timeout i will contain 0xffffffff and not 0. Thus in turn will fool the following if-statement leading to wrong return value to the caller in this case. Therefore the caller will see a received character event if there is none. Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18binaryPI: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18AGESA: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-05-18AMD MTRR: Add common add_uma_resource_below_tolm()Kyösti Mälkki
Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-18CBMEM: Add config CBMEM_TOP_BACKUPKyösti Mälkki
AGESA and binaryPI boards have no easy way to determine correct cbmem_top() location early enough when GFXUMA is enabled, so they will use these functions with EARLY_CBMEM_INIT as well. At the end of AmdInitPost() the decisions of UMA base and size have not been written to hardware yet. The decisions are stored inside AGESA heap object we cannot locate from coreboot proper until after AmdInitEnv(). Modify code such that weak backup functions are only defined for LATE_CBMEM_INIT; they are somewhat troublesome to handle. Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-18intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi
In the intel/common/block * Move I2C common code from intel/common to intel/common/block. * Split the code into common, early init and post mem init stages and put it in lpss_i2c.c, i2c_early.c and i2c.c respectively. * Declare functions for getting platform specific i2c bus config and mapping bus to devfn and vice versa, that have to be implemented by SoC. In skylake/apollolake * Stop using code from soc/intel/common/lpss_i2c.c. * Remove early i2c initialization code from bootblock. * Refactor i2c.c file to implement SoC specific methods required by the I2C IP block. Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18google/scarlet: Enable innolux,p079zca MIPI panelNickey Yang
TEST=Boot from scarlet, and mipi panel works Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: Add MIPI driverNickey Yang
This patch configures clock for mipi and then adds mipi driver for support innolux-p079zca mipi panel in rk3399 scarlet. Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: remove the delay for enabling SSCCaesar Wang
The hang was caused by deasserting the reset before, it had been delayed 20us fixing the hang issue. So we can remove this delay for now. Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-17siemens/mc_apl1: Program eMMC DLL settingsMario Scheithauer
Program eMMC DLL settings for mc_apl1 mainboard, after that system can boot up with eMMC successfully. Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-17siemens/mc_apl1: Select external 8250 UARTMario Scheithauer
The mainboard siemens/mc_apl1 uses an external I/O port for console output. For this reason we need to activate the 8250 LPC UART. Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17soc/intel/apollolake: Enable decoding for ComA and ComB on LPCMario Scheithauer
If there is an external 8250 UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Furthermore FSPM needs different settings for an external UART port. For this, the function fill_console_params() has to be adapted. Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17mb/google/eve: Remove FPC device from SPI1Duncan Laurie
This device is no longer directly connected to the SOC so it does not need to be enabled in coreboot. BUG=b:35648259 TEST=build and boot on Eve Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19728 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mb/google/eve: Update touchpad I2C timingDuncan Laurie
The touchpad frequency was still slightly above 400kHz so tweak the timing values manually to get under the spec limit. BUG=b:35583133 TEST=verified the bus frequency with a scope to be < 400kHz Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19727 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mainboard/google/poppy/variants/soraka: Enable H1 I2C TPMFurquan Shaikh
1. Add a separate devicetree file for soraka variant and add H1 node. 2. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19519 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17mainboard/google/poppy: Correct I2C bus number for TPMFurquan Shaikh
TPM is on I2C bus 1. Fix that. BUG=b:36265511 Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19710 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17google/fizz: Configure SATAXPCIe GPIOs to use native functionShelley Chen
BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-05-16soc/intel/common: Add sanity check of PCR_BASE_ADDRESSLijian Zhao
PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero default value. TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and build. BUG=None Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-16soc/intel/skylake: Add option to enable/disable EISTSubrata Banik
Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-16soc/intel/skylake: Configure C-state interrupt response timeSubrata Banik
Program C3/C7/C10 interrupt response time for all cores. Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-16cpu/intel/turbo: Add option to disable turboSubrata Banik
disable_turbo function can be used to disable turbo mode on each processor by settings MSR 0x1A0 bit 38. This option will help to perform some quick test without enabling turbo mode. Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-16arch/arm64: Use variables of the right size for msr/mrs opcodesPatrick Georgi
They do 64bit accesses, and gcc does the necessary fix ups to handle 32bit values as zero-padded 64bit values. clang, however, isn't happy with it. Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/19661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-15vexpress: change to write32Vladimir Serbinenko
Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/19685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-13vexpress: add gfx initVladimir Serbinenko
Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-13src/include/device: Add PCIe root ports device idsAamir Bohra
Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19664 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-13drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.cNico Huber
And don't link it. It's for ROMCC. To make code happy that uses the ROMCC interface read_option(), read_option_lowlevel() is ported to mc146818rtc.c along with a message to use get_option() instead. Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-13mainboard: Add ASRock G41C-GSArthur Heymans
Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-13nb/intel/x4x: Fix uninitialized variable issueNico Huber
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not supported). Should fix coverity issue 1375009. Remove a redundant line that uses the variable `gfxsize` out of its scope and move the variable declaration. Make sure the variable is always initialized, drop unneeded error-handling for `get_option()` and sanitize the read value instead. Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19680 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-12mb/gigabyte/ga-g41m-es2l: Don't disable PATAArthur Heymans
This board features a PATA port. TESTED PATA drive works in SeaBIOS and OS. Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-12mainboard/google/reef: Config needed GPIO for pull-up WALijian Zhao
This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-12soc/intel/apollolake: Add macro to define IOSTERM for GPIO configLijian Zhao
Add macro to config GPIO IOSTERM bits. BUG=b:37998248 Change-Id: I178f6d3055d4620cb3c895245c40f324383873ad Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19576 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-12drivers/storage: Delay after SD SWITCH operationsLee Leahy
Delay for a while after the switch operations to let the card recover. TEST=Build and run on Galileo Gen2 Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-12qemu/vexpress-a9: Discover RAM size.Vladimir Serbinenko
Probe RAM to find its size instead of hardcoding 1024M. Also properly export it to memory map. Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-12intel/common: drop duplicate initializerPatrick Georgi
Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: clang Reviewed-on: https://review.coreboot.org/19656 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-12vendorcode/intel/fsp/fsp2_0/glk: Add FSP header files for GLKHannah Williams
from FSP release V030_61 Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19605 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-11nb/intel/gm45: Fix raminit with mixed raw card typesTristan Corrick
`cardF[n]` should indicate whether the DIMM in channel n is of raw card type F. However, `cardF[1]` was initialised with the value meant for `cardF[0]`. This patch results in the correct initialisation of `cardF`. Tested on a Lenovo T400 containing two DIMMs: one of raw card type F and the other of raw card type B. Before the patch, the system would not boot. After the patch, the system boots with all of the memory functional. Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552 Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com> Reviewed-on: https://review.coreboot.org/19652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-11nb/intel/gm45: Fix some errors/warnings given by checkpatchTristan Corrick
This results in raminit_receive_enable_calibration.c producing no errors or warnings with checkpatch. The issues fixed are: ERROR: that open brace { should be on the previous line WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Tested by compiling after making the changes. Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78 Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com> Reviewed-on: https://review.coreboot.org/19651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-11mainboard/pcengines/apu2: Add LPC TPM supportPhilipp Deppenwiese
APU2 exposes a LPC header which can be used in conjunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-11amd/pi: Add AMD fam16h TPM ACPI path supportPhilipp Deppenwiese
Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-11mb/sapphire/pureplatinumh61: Sanitize KconfigNico Huber
Remove overrides that set platform defaults or insane values. Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2017-05-11siemens/mc_apl1: Add usage of external RTC RX6110 SAMario Scheithauer
This mainboard contains an external RTC chip RX6110 SA. Enable usage of this chip and set some initialization values to device tree. Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-11drivers/i2c: Add new driver for RTC type RX6110 SAMario Scheithauer
This driver enables the usage of the external RTC chip RX6110 SA (http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in the device tree so that the used setup can be adapted to match the configuration of the device on the mainboard. Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-11mb/lenovo/x60/t60: Remove `fn_ctrl_swap` optionNico Huber
The EC doesn't support it. Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-11mb/lenovo/x201: Add support for ThinkLightStefan Ott
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the ThinkLight from the Operating System. This patch adds partial support for that method, enough to enable or disable the ThinkLight: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light With the original BIOS the UCMS method exposes a wide range of values through a generic /proc/acpi/ibm/cmos interface. With the changes suggested in this patch that interface is also exposed but only accepts the commands to enable or disable the ThinkLight; all other commands are ignored. This change would potentially benefit all currently supported Thinkpad models, I only have an X201 available for tests though. Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/19644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-11superio/nuvoton: Make SuperIO config functions externally availableArthur Heymans
Change-Id: I05f768c67542770e65279a562c05225b84edca40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-11nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
Currently only one board uses this northbridge in coreboot but some patches are pending to add more. Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11nb/intel/gm45: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11nb/intel/i945: Define and use a default MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11siemens/mc_apl1: Correct GPIO settingsMario Scheithauer
- set GPIO_183 to high level for enabling the power of SD card - delete all GPIOs for JTAG interface because they lead to problems with Lauterbach debug hardware Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 08:29:11 +0000