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2010-11-21Convert more boards to use mptable_write_buses.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Convert boards to use mptable_write_buses.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs werePatrick Georgi
not brought over to Kconfig (this applies to all #defines to 4, as that's the default anyway) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Use DIMM0 et al in lots more places instead of hardocding values.Uwe Hermann
The (0xa << 3) expression equals 0x50, i.e. DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Build fix.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Merge all spd_addr.h into the resp. romstage.c files.Uwe Hermann
Except for one instance the spd_addr.h were now very tiny, there's not much point in keeping that stuff in an extra file. The only user of those files is the romstage.c file anyway. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Unify DIMM SPD addressing. For Geode, change thePatrick Georgi
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-19Cosmetic fixes and comment additions in acpi.c.Uwe Hermann
- Fix whitespace, coding style, and indentation in some places. - Add comments for less obvious entries and hardcoded numbers (e.g. 'type'). - Add comments for all/most 'revision' fields, mention in which version of the ACPI spec which revision number is to be used. - Add URLs to a few external documents which describe tables that are not mentioned in the ACPI spec (or where the external document may provide further info), e.g. SRAT, SLIT, HPET, MCFG, etc. - Use the ASLC #define instead of hardcoding "CORE" in one instance (ASLC is already used everywhere else). - Add some TODOs for additional stuff which is in the spec but not yet handled by our code / #defines. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Fix/drop some obsolete comments,Uwe Hermann
- s/Options.lb/devicetree.cb/ - s/Config.lb/devicetree.cb/ - s/cache_as_ram_auto.c/romstage.c/ - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in the tree now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Drop unused and incorrect RTC_DEV for Winbond W83627EHG.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Move DIMM_MAP_LOGICAL to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Move register block definitions out of board code intoPatrick Georgi
chipset code (where it belongs) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18For completeness sake: License header.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Eliminate SET_NB_CFG_54 option. There was no board thatPatrick Georgi
deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17Dynamically generate PNP0C02 mainboard resources in SSDTTobias Diedrich
Updated patch with improved comments and small bugfix (use same value for min and max on io resource). While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded. This is a proof of concept patch for the M2V board that dynamically creates a ResourceTemplate() containing these in the SSDT and adds a corresponding PNP0C02 device to the DSDT. All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set are added. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Added M2V-MX SE too. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17Linux also needs the MMCONF area to be reserved either in E820 orTobias Diedrich
as an ACPI motherboard resource or it will not enable MMCONFIG and the extended pcie configuration area will be unaccessible: This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF resource flags to do this. I also added a new resource for the mapped bios rom area just below 4GB. I'm not sure if the choice for the index parameter of new_resource() is correct though. Note that the bios rom decode is enabled in src/southbridge/via/vt8237r/vt8237r_early_smbus.c for the whole 4MB area (even though the comment says 1MB). Ruik: I extended the flash range to 16MB (This is what VT8237S can decode) Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete) Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17This problem was introduced withTobias Diedrich
http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17The only southbridge having a pirq_assign_irqs function (needed forTobias Diedrich
CONFIG_PIRQ_ROUTE) so far is the amd cs5530. Add one for vt8237 too. Setting up the pci routing is important in case you want to boot DOS, OSes that don't support ACPI or MP tables and ROMs for add-in storage controllers may depend on this too. TODO: Fix the 4 routing links limitation in src/arch/i386/boot/pirq_routing.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Drop W83627THF, it's the same device as W83627THG.Uwe Hermann
The only difference is that the "G" version is in a Pb-free package, which is not relevant from a programmer's view. We keep W83627THG (and drop W83627THF) because: - The W83627THF had a CIR device / LDN which doesn't actually exist. - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out). - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards. This also fixes an issue on MSI MS7135's devicetree.cb: device pnp 4e.6 off end # XXX keep allocator happy The line above can be (and is) removed, as it was only needed due to the incorrect CIR LDN in the W83627THF. In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Drop commented out debug definesPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Forgot to remove one set of SET_FIDVID definesPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Move the SET_FIDVID* family of configuration options to Kconfig andPatrick Georgi
make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16back out parts of #6073Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15fix random breakageStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15Move RCBA defines to northbridge (instead of mainboard)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15C and other Super I/O cosmetic fixes.Uwe Hermann
- Random coding style, whitespace and cosmetic fixes. - Consistently use the same spacing and 4-hexdigit port number format in the pnp_dev_info[] arrays. - Drop dead/unused code and less useful comments. - Add missing "(C)" characters and copyright years. - Shorten and simplify some code snippets. - Use u8/u16/etc. everywhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14Add a target for the ASUS A8V-E Deluxe (trivial).Uwe Hermann
For now this is a plain copy of the ASUS A8V-E SE target, I reported that most of the code also works (sort of) for the ASUS A8V-E Deluxe a long while ago, see http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html http://www.coreboot.org/ASUS_A8V-E_Deluxe There will be a bunch of changes necessary though (devicetree.cb, mptable.c, ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target. Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as otherwise there will be build errors if the MAINBOARD_PART_NUMBER string gets too long (as is the case for "A8V-E Deluxe"). The error is: ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps section .romstrap loaded at [00000000ffffff80,00000000ffffffd3] (both with stock Debian gcc and with xgcc) Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14CK804/MCP55 devicetree.cb cosmetic and indentation fixes.Uwe Hermann
Add a few more comments for the entries, and also change the devicetree.cb files to the more compact and better readable variant with indentation level of 2 spaces (instead of random mix of tabs and spaces). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14Return 0, (as for 40pin cable if SB not found)Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14Move cable detect logic to a weak function in vt8237r_ide.c and addTobias Diedrich
an override function in m2v/mainboard.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14Currently the Tobias Diedrich
cablesel |= (sb->ide0_80pin_cable << 28) | (sb->ide0_80pin_cable << 20) | (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); in vt8237r_ide.c ends up doing cablesel |= 0xfffffff0; (with both bits set to 1) which is probably not the intended result. ;) After a short discussion on irc the consensus was to change the bitfields to u8 as it's probably not worth it using bitfields here. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
-- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-12mainboard/asus/m2v: Set DDR2 voltage to 1.8VTobias Diedrich
The power-on default is 1.95V, set the DDR2 voltage to standards-conforming 1.8V. I also measured with a multimeter to confirm this. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11Add support for Fintek F71872 superio.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11Remove superfluous Super I/O res0/res1 lines.Uwe Hermann
The pc_keyboard_init() function no longer takes any base addresses since r5152 (passed in via res0/res1 variables previously), so drop them. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11Add VT8237A id to src/southbridge/via/vt8237r/bootblock.cTobias Diedrich
I missed this one since it was working anyway, since "The LPC BIOS ROM is always accessed when ISA addresses FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet) And the rom I use for testing is smaller than this 512KB default range. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11Add pci id and ops for VT8237A SATA controllerTobias Diedrich
Needed to change class from raid to ide so seabios can boot from it. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Use the new mptable_write_buses() on the ASUS M2V.Tobias Diedrich
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Add mptable for ASUS M2V.Tobias Diedrich
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Restructure i3100 Super I/O driver to match the rest of the codebase.Uwe Hermann
- i3100_early_serial.c: - Split out enter/exit functions as the other Super I/Os do. - Make i3100_enable_serial() take a device_t as usual, and convert it to use the standard pnp_* function instead of open-coding the same functionality by hand. - Factor out i3100_configure_uart_clk() from i3100_enable_serial(), we do the same in various other Super I/Os, e.g. ITE ones. - Add some #defines for register / bit values and some comments. - Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's marked as "READ ONLY, WRITES IGNORED" in the datasheet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Random Winbond Super I/O cosmetic and coding-style fixes.Uwe Hermann
- Whitespace, coding style, and typo fixes. - Drop unused/obsolete "#config chip.h". - Use u8/u16/etc. everywhere. - Use pnp_read_config()/pnp_write_config() instead of open-coding them. - Use pnp_set_logical_device() instead of open-coding it. - W83627EHG: Fix incorrect enable_hwm_smbus() code comment. - Use ARRAY_SIZE. - w83627hf/superio.c: w83627hf_16_bit_addr_qual(): Bugfix, the code was using 'dev->path.pnp.port >> 8' as config port, which is incorrect in superio.c (which has a "real" device_t struct, in contrast to *_early_serial.c which uses "unsigned" as device_t where 'dev >> 8' is required). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Make amdk8 printk_raminit() accept just a single string parameterPeter Stuge
The function is called with no format specifiers in the first parameter throughout the code, so it needs to work also with just one parameter. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG()Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Debugging facility improvements.Uwe Hermann
- Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in menuconfig if at least DEBUG or SPEW are selected as loglevel, as this code does additional printk(BIOS_DEBUG, ...) calls which would otherwise not be visible anyway. - Similarly, make DEBUG_CAR and REALMODE_DEBUG only visible if thr DEBUG or SPEW loglevel is selected. - Get rid of a custom "debug" macro, use printk() as usual. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10ITE IT8661F changes to match the common code structure.Uwe Hermann
- it8661f_enable_serial() is now in the usual format, using pnp_* functions. - Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode(). - Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz. - Factor out it8661f_enable_logical_devices(), might not be needed though. We leave it here until it's confirmed on hardware that it's not needed. - Move some #defines to it8661f.h. - Drop no longer used it8661f_sio_write(). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up theTobias Diedrich
Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of address space. Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09Add acpi tables and dsdt.Tobias Diedrich
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09Add pirq table for ASUS M2V.Tobias Diedrich
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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