Age | Commit message (Expand) | Author |
2015-04-10 | veyron*: sdram_get_ram_code() -> ram_code() | David Hendricks |
2015-04-10 | veyron*: use gpio_base2_value() in board_id() | David Hendricks |
2015-04-10 | veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5V | Julius Werner |
2015-04-10 | veyron_jerry: Remove board ID based assumptions | Julius Werner |
2015-04-10 | veyron: Change eMMC enable pin to be pulled (not driven) high | Doug Anderson |
2015-04-10 | Add google/veyron_jerry board | Katie Roberts-Hoffman |
2015-04-10 | storm: copy WiFi calibration data in the CBMEM | Vadim Bendebury |
2015-04-10 | tegra132: psci: add cpu_on/off support | Joseph Lo |
2015-04-10 | arm64: No need of invalidating cache line for secondary CPU stack | Furquan Shaikh |
2015-04-10 | arm64: Add support for save/restore registers for CPU startup. | Furquan Shaikh |
2015-04-10 | arm64: Add macro to invalidate stage 1 TLB entries at current EL | Furquan Shaikh |
2015-04-10 | arm64: Add conditional read/write from/to EL3 assembly macros. | Furquan Shaikh |
2015-04-10 | arm64: Add function for reading TCR register at current EL | Furquan Shaikh |
2015-04-10 | tegra132: Make non-vboot2 memlayout more useful | Furquan Shaikh |
2015-04-10 | tegra132: Change memlayout to have PRERAM and POSTRAM CBFS Cache | Furquan Shaikh |
2015-04-10 | tegra132: Bump up ramstage to 256K | Furquan Shaikh |
2015-04-10 | google/rush_ryu: Add speaker amp config for AD4567 on P0/P1 | Tom Warren |
2015-04-10 | tegra132: prepare cpu startup in psci | Aaron Durbin |
2015-04-10 | arm64: psci: actually inform SoC layer of CPU_ON entry | Aaron Durbin |
2015-04-10 | google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSI | Jimmy Zhang |
2015-04-10 | tegra132: Increase size of bootblock due to overflow | Tom Warren |
2015-04-10 | arm64: ensure secondary CPU's stack tops are not in the cache | Aaron Durbin |
2015-04-10 | arm64: add timeout waiting for CPUs to come online | Aaron Durbin |
2015-04-10 | tegra132: always bring up PLLD | Aaron Durbin |
2015-04-10 | tegra132: rename clock_display() to clock_configure_plld() | Aaron Durbin |
2015-04-10 | google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc. | Tom Warren |
2015-04-10 | tegra132: Set dc to resize the difference between framebuffer and panel | Jimmy Zhang |
2015-04-10 | google/rush_ryu: devicetree: Add framebuffer resolution settings | Jimmy Zhang |
2015-04-10 | tegra132: Add framebuffer parameters | Jimmy Zhang |
2015-04-10 | tegra132: Pass panel spec to lib_sysinfo | Jimmy Zhang |
2015-04-10 | tegra132: Expand ramstage size to 208k (from 192k) | Jimmy Zhang |
2015-04-10 | tegra132: Add dsi driver | Jimmy Zhang |
2015-04-10 | google/rush_ryu: devicetree: Add dsi panel mode settings | Jimmy Zhang |
2015-04-10 | tegra132: Add panel mode spec | Jimmy Zhang |
2015-04-10 | google/rush_ryu: dsi: Enable panel related vdd and clocks | Jimmy Zhang |
2015-04-10 | google/rush_ryu: Disable EC SW sync for proto boards before proto3 | Furquan Shaikh |
2015-04-10 | tegra132: Increase space for romstage in memlayout | Furquan Shaikh |
2015-04-10 | urara: support building with CHROMEOS enabled | Vadim Bendebury |
2015-04-10 | baytrail: correct NC pin to GPO pin according to BYT platform design guide | Kane Chen |
2015-04-10 | samus: Log EC panics to eventlog | Shawn Nematbakhsh |
2015-04-10 | cros_ec: Retry failed VBNV transactions | Julius Werner |
2015-04-10 | samus: Enable vr_slow_ramp | Shawn Nematbakhsh |
2015-04-10 | x86: Support reset routines in bootblock | Lee Leahy |
2015-04-10 | broadwell: Correct XHCI offset for USB 3.0 ports | Julius Werner |
2015-04-10 | broadwell: Set PCIe replay timeout to 0xD | Duncan Laurie |
2015-04-10 | samus: Use codec internal 1.8V as DACREF source | Ben Zhang |
2015-04-10 | samus: Set MICBIAS1 to 2.970V | Ben Zhang |
2015-04-10 | baytrail: add code for supporting 2x ddr refresh rate | Kane Chen |
2015-04-10 | broadwell: Add configuration for tuning VR for C-state operations | Duncan Laurie |
2015-04-10 | samus: Adjust SATA Gen3 TX voltage amplitude | Duncan Laurie |