summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1146 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/642 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/640 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Add generic IOAPIC driverSven Schnelle
Used for automatic generation of IOAPIC interrupt entries. Change-Id: Ia746f01906c840800956ce551306f864e440b6ec Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1137 Tested-by: build bot (Jenkins)
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
Default CPU_ADDR_BITS is 36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/639 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Supermicro X7DB8: add w83793 Hardware monitorSven Schnelle
used for fan control and thermal management on that board. Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1167 Tested-by: build bot (Jenkins)
2012-07-04Add Nuvoton W83793 hardware monitor driverSven Schnelle
Change-Id: I3ecb5c8666eea247bf4c31aaf9426bd9ef66bf68 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1166 Tested-by: build bot (Jenkins)
2012-07-03Fix AMD S3 block generator on CygwinPatrick Georgi
awk on Cygwin created the UTF-8 value for the 0xff code point, which makes it two bytes wide. This broke the build. Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1164 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-03SMBIOS: move serial number and version out to KconfChristian Gmeiner
With this change it is possible to define serial number and version of the mainboard. These informations are used in SMBIOS tables. Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1163 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03Fix the error message for romstage when .bss or .data are non-zeroRonald G. Minnich
The error message from romstage is annoying and misleading: "Do not use global variables in romstage" Because it can occur even when global variables are not used in some circumstances, but also because it gives you only a rough idea where to look. This change sucks but sucks less. We still don't know which file the problem is in but at least we know if it is data or bss. Replace the error message with something that provides more information and less guessing on the part of the script: ".bss is non-zero size in romstage which is not allowed -- global variable?" or ".data is non-zero size in romstage which is not allowed -- global variable?" To test: build coreboot as normal. It builds. Add char d[32]; to romstage.c and get the first error message; add int x = 32; to romstage.c and get the second. Change-Id: I300ec05bdb4b30d7ef3f5112e6cc09b1fafe8263 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1160 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15tn: AMD family15 AGESA code for Trinityzbao
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-24X60/T60: fix mptable LINT entriesSven Schnelle
They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE. While at it, uses mptable_lintsrc() instead. Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1136 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-23Add Supermicro X7DB8 motherboardSven Schnelle
This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/493 Tested-by: build bot (Jenkins)
2012-06-23i3100: add smbus_write_byte()Sven Schnelle
Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1116 Tested-by: build bot (Jenkins)
2012-06-23Add an option for Waiting for gdb connection if the gdb stub configuration ↵Denis 'GNUtoo' Carikli
is chosen. Here's a quick demonstration on how to use it(tested on M4A785T-M). (gdb) file ./build/cbfs/fallback/coreboot_ram.debug Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done. (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyUSB0 Remote debugging using /dev/ttyUSB0 _text () at src/arch/x86/lib/c_start.S:85 85 call hardwaremain Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21i3100: Enable second IOAPIC for PCI-XSven Schnelle
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X. Add code to enable it. Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21Don't use 64-bit constant 0x100000000 in linker scriptsNico Huber
The constant value 0x100000000 is used in linker scripts to calculate offsets from the end of 32-bit-addressed memory. There is nothing wrong with it, but 32-bit versions of ld do the calculation wrong. Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-20i5000: fix another typoSven Schnelle
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid. Let's do another typo fix... Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1119 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-06-20i5000: fix typosSven Schnelle
Peter and Ron pointed out two typos. They have no side effects, but it's still worth to fix them. Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1117 Tested-by: build bot (Jenkins)
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
Those CPUs support the PECI (Platform Environment Control Interface), so enable it. This interface is commonly used for tasks like fan control. Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1104 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-06-18i5000: enforce hard resetSven Schnelle
Not doing a hard reset leaves the BOFL0 register cleared, which prevents the BSP selection from working. To make sure we start with known values, use the SPAD0 register for soft reset detection. If there's a value other than 0, do a hard reset. Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1103 Tested-by: build bot (Jenkins)
2012-06-14llshell: fix build without romccDenis 'GNUtoo' Carikli
Without that fix we have: LINK cbfs/fallback/romstage_null.debug build/generated/crt0.romstage.o: In function `ramtest': romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt' collect2: ld returned 1 exit status make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1 On the M4A785T-M which doesn't have CONFIG_ROMCC. Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1101 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-06-12Update SB800 CIMX FADTMartin Roth
- Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1055 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-06-12udelay: add missing bus frequencySven Schnelle
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1099 Tested-by: build bot (Jenkins)
2012-06-01Enable CONFIG_GFXUMA for roda/rk886exNico Huber
Without GFXUMA beeing set, MTRR initialization runs out of variable MTRRs. Change-Id: I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-30Initializer of a static member in union.zbao
It is just me or does anybody have the same build error without this patch? ------ src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC': src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv' specified in initializer src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around initializer src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization for 'addr.<anonymous>') ------- Anyway, I believe at least this will cause warnings. "resv" is a member of a union, not of acpi_addr_t. So it should be wrapped by a brace in the initializer. Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-30Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli
Without that fix the debugging is harder because the person debugging coreboot will see the following twice(note the repeated MTRR number): Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC instead of the following twice: Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea: May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs() Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1058 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-05-30Provide functions to access arbitrary GPIO pins and vectorsVadim Bendebury
This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1049 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-30Add support for Panther Point to SPI driverStefan Reinauer
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1048 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-29Use ld manually when compiling with clangPatrick Georgi
clang does its own linking, incompatible to our binutils-centric linker magic. Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Fix compilation with CONFIG_DEBUG_SPI_FLASH enabledStefan Reinauer
Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Fix full reset for Ivy Bridge platformsVadim Bendebury
Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1050 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29ChromeOS: Remove remnants of FDT supportStefan Reinauer
Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1051 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-28Enable USE_OPTION_TABLE for ThinkPad X60Motiejus Jakštys
Without this option bluetooth configuration value in nvram is not consulted properly. It also enables built-in volume control (read-only). Tested on: ThinkPad X60s, 1702. Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d Signed-off-by: Motiejus Jakštys <desired.mta@gmail.com> Reviewed-on: http://review.coreboot.org/985 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-05-26Implement %zu / %zd in printkStefan Reinauer
The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-26Move subsystem IDs to devicetree.cbStefan Reinauer
A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-26Reduce default verbosity of SPI flash driversStefan Reinauer
Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1045 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-26Fix printk types in SPI flash driversStefan Reinauer
- use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1041 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-25Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUMEMarc Jones
Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1054 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-05-25Fix size_t for certain versions of GCCStefan Reinauer
When compiling coreboot with the latest ChromeOS toolchain, GCC complains that some printk calls use %zu in connection with size_t types since it resolves the typedefs to long unsigned int. The problem is solved by using the GCC built-in __SIZE_TYPE__ if it exists and define __SIZE_TYPE__ to long unsigned int otherwise. Change-Id: I449c3d385b5633a05e57204704e981de6e017b86 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1040 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-24Converted the FRAMEBUFFER_VESA_MODE to a choice.Steve Goodrich
Being a diligent soul, I changed the "enter a numeric value for the mode you want" option to a choice of common modes. New modes can be added quite easily. Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/1036 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/912 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-21Fix Persimmon build without S3.Marc Jones
In the heap function, only check for S3 check when it is built in with CONFIG_HAVE_ACPI_RESUME. Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1034 Tested-by: build bot (Jenkins) Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>