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AgeCommit message (Expand)Author
2014-05-13baytrail: add C0 microcode updateAaron Durbin
2014-05-13baytrail: reboot with EC in S0 with no MRC cache and EC in RWAaron Durbin
2014-05-13chromeec: add function to reboot on unexpected imageAaron Durbin
2014-05-13baytrail: dptf: Add disable trip point methodsDuncan Laurie
2014-05-13rambi: dptf: Set critical thresholdsDuncan Laurie
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
2014-05-13baytrail: Updates for DPTF ACPI frameworkDuncan Laurie
2014-05-13chrome ec: Update header and add functions to support DPTFDuncan Laurie
2014-05-13rambi: Update the DPTF configurationDuncan Laurie
2014-05-13baytrail: don't SMI on tco timer firingAaron Durbin
2014-05-13baytrail: clear the pmc wake status registersAaron Durbin
2014-05-13baytrail: log reset, power, and wake events in elogAaron Durbin
2014-05-13baytrail: snapshot power state in romstageAaron Durbin
2014-05-13baytrail: add cpuid for C0Aaron Durbin
2014-05-13rambi: Move KBD_IRQ pin for Rambi 2.0 boardShawn Nematbakhsh
2014-05-13src/*: Remove the last remnants of struct keyboardEdward O'Callaghan
2014-05-13superio/*: Remove redundant chip.h headerEdward O'Callaghan
2014-05-13superio/*: Deal with some chip.h special casesEdward O'Callaghan
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
2014-05-13southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridgeEdward O'Callaghan
2014-05-12Rambi: Enable 32k SUSCLK signalKyösti Mälkki
2014-05-12rambi: Make eMMC CLK pull-down and change pull strengths to 20KShawn Nematbakhsh
2014-05-12baytrail: align with intel recommendationsAaron Durbin
2014-05-12rambi: specify reference code index in vboot areaAaron Durbin
2014-05-12baytrail: add way to load reference code from vboot areaAaron Durbin
2014-05-12baytrail: Expose IOSF as ACPI objectDuncan Laurie
2014-05-12rambi: Disable HSUART2 and SPI interfacesDuncan Laurie
2014-05-12rambi: Enable SCC devices in ACPI modeDuncan Laurie
2014-05-12baytrail: Put devices in ACPI mode after setupDuncan Laurie
2014-05-12baytrail: Add header include wrapper and offset defineDuncan Laurie
2014-05-12superio/ite/it8718f: Remove hard coding from romstageEdward O'Callaghan
2014-05-11superio/ite/*: Factor out generic romstage componentEdward O'Callaghan
2014-05-11superio/ite/it8728f: RAMstage PNP configuration componentEdward O'Callaghan
2014-05-11SeaBIOS: Fix cpp usePatrick Georgi
2014-05-10Arch-level Kconfig menu cleanupFurquan Shaikh
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-10mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cbEdward O'Callaghan
2014-05-10superio/fintek/f71869ad: Fix incorrect LDN'sEdward O'Callaghan
2014-05-10baytrail: cache reference code for S3 resumeAaron Durbin
2014-05-10baytrail: allow ramstage_cache_location() usage in ramstageAaron Durbin
2014-05-10ramstage_cache: allow ramstage usage add valid helperAaron Durbin
2014-05-10baytrail: note S3 resume status earlierAaron Durbin
2014-05-10baytrail: utilize reg_script_run_on_dev()Aaron Durbin
2014-05-10baytrail: initialize perf/power registersAaron Durbin
2014-05-10baytrail: add more iosf access functionsAaron Durbin
2014-05-10baytrail: remove verbosity in iosfAaron Durbin
2014-05-10reg_script: add reg_script_run_on_dev()Aaron Durbin
2014-05-10baytrail: Add support for LPSS and SCC devices in ACPI modeDuncan Laurie
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
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