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2015-09-04mc_tcu3: Adjust gpio settingsWerner Zeh
Adjust gpio settings due to hardware change. Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11489 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-03mc_tcu3: Extend hwinfo.hex and remove version.hex.Werner Zeh
1. Update hwinfo.hex (add dummy data and update checksums). 2. Delete version.hex from mainboard directory. It can be added in site-local if needed. Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-02southbridge/ibexpeak: use new ssdt sata port generatorAlexander Couzens
Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9710 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-09-02southbridge/bd82x6x: use new ssdt sata port generatorAlexander Couzens
Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9709 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-31northbridge/intel/gm45/Kconfig: Remove IOMMU symbol choiceMartin Roth
In the gm45 code, IOMMU is always selected to be enabled. Instead this patch removes the Kconfig symbol and its dependencies. This leads to the same effect without the need for the symbol. The symbol is still used in the K8 code as it's not selected, simply defaulted to being enabled, and one of the mainboards disables it. Change-Id: Ibc5939cd1e297d497bf71b1787d852f7cc09a551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11345 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-08-31drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macroAlexandru Gagniuc
Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11464 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-31soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEMAlexandru Gagniuc
This depends on RELOCATABLE_RAMSTAGE, and shouldn't be selected if its dependency is not activated. Change-Id: I8e7efc3f87e105715fe3377ed306891f0d209979 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11473 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-31timestamp: add tick frequency to exported tableAaron Durbin
Add the timestamp tick frequency within the timestamp table so the cbmem utility doesn't try to figure it out on its own. Those paths still exist for x86 systems which don't provide tsc_freq_mhz(). All other non-x86 systems use the monotonic timer which has a 1us granularity or 1MHz. One of the main reasons is that Linux is reporting /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true turbo frequency on turbo enables machines. This change also fixes the p-state values honored in cpufreq for turbo machines in that turbo p-pstates were reported as 100MHz greater than nominal. BUG=chrome-os-partner:44669 BRANCH=firmware-strago-7287.B TEST=Built and booted on glados. Confirmed table frequency honored. Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31imgtec/pistachio: remove timestamp_get() implementationAaron Durbin
As pistachio already provides timer_monotonic_get() let the generic timestamp_get() use that instead of having around another implementation of timestamp_get(). BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: Iaa6db49f0055b7c2ef116f41453f838093e516e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11469 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-31armv7/arm64: remove timestamp.cAaron Durbin
The src/lib/timestamp.c already has an implementation using timer_monotonic_get() for timestamp_get(). Use that instead of duplicating the logic. BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: If17be86143f217445bd64d67ceee4355fa482d39 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-31AMD bettong: Fix the PCIe lane mapzbao
Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31AMD Bettong: Set the USB3 port as unremoveable.zbao
Without this change, if one USB3 device is attached when the board is power up, the USB3 port can not be used. Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31AMD Bettong: Lower the TOM to give more MMIO spacezbao
Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE KconfigAlexandru Gagniuc
This option was removed in the following commit: * 80f5d5b fsp1_1: remove duplicate mrc caching mechanism Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-31drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairsAlexandru Gagniuc
The #error messages only say that "CONFIG_* must be defined", which conveys no more information that the compiler or assembler failing when it encounters an undefined CONFIG_* symbol. Change-Id: I6058474d4cd454cfc20290650425d379f388abd9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11461 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-30Kconfig: Remove EXPERT modeAlexandru Gagniuc
After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-08-30Kconfig: Don't 'select' options based on PAYLOAD_SEABIOSAlexandru Gagniuc
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11293 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2015-08-29intel/kunimitsu: Export EC_IN_RW for depthcharge/vbootzhuo-hao
Reference CL:294712 BUG=chrome-os-partner:43072,chrome-os-partner:43707 BRANCH=none TEST=build coreboot and boot on Kunimitsu Fab3.1 Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92 Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295514 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: port the change from glados for correctly reading lidrobbie zhang
switch and SPI write protect for fill_lb_gpios() to coreboot table. BUG=chrome-os-partner:43707 BRANCH=none TEST=build and boot on kunimits Signed-off-by: robbie zhang <robbie.zhang@intel.com> Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680 Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5 Original-Reviewed-on: https://chromium-review.googlesource.com/295580 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Remove unnecessary check for mainboard_ec_init()Martin Roth
mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: port the change from glados for enabling readingrobbie zhang
recovery mode. BUG=chrome-os-partner:43683 BRANCH=none TEST=build and boot on kunimits and successfully enter recovery mode by pressing “Esc + refresh + Power” keys. Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61 Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295138 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11434 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: Adding mainboard init to enable SCI eventpchandri
BUG=chrome-os-partner:44470 BRANCH=None TEST=Builds and Boots on FAB3 (Kunimitsu) Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8 Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295218 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: fix SCI handlingWenkai Du
Ported below patch from glados to kunimitsu: glados: Abstract board GPIO configuration in gpio.h Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Originally-signed-off-by: Duncan Laurie <dlaurie@chromium.org> Originally-reviewed-on: https://chromium-review.googlesource.com/293942 BUG=chrome-os-partner:40828 BRANCH=none TEST=Verify that acpi interrupts are incrementing on kunimitsu. Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295048 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11432 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: fix kepler probingWenkai Du
The patch was ported from commit: glados: fix kepler probing BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted kunimitsu. lscpi shows the device on bus 2. Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Originally-signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810 Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11431 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Add support for DPTFShilpa Sreeramalu
This patch adds the ASL files with the DPTF related settings and the thermal devices enabled in the SOC. It also enables the DPTF setting at the global NVS level. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7 Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11430 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: Enable and support for DPTFShilpa Sreeramalu
This patch includes the DPTF specific ASL files in the main DSDT definition and enables the CPU thermal participant device in the device tree. It also enables the DPTF flag in the global NVS table.It also adds the ASL settings specfic to the mainboard. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284821 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294650 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11429 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: clean up ec smi and make EC_SMI_L functionalrobbie zhang
forward port of "glados: make EC_SMI_L functional", commit 50ed38feba58f BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08 Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295045 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11428 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/sklrvp: Switch to using GPIO IRQ definesDuncan Laurie
Use the macro for GPP_E22_IRQ instead of the ACPI code so it can be removed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5 Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295171 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpiorobbie zhang
config to coreboot completely BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I78e16e8079c4ee0c4fa70cb7a74ba039ee89398f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6f1db1a2ffdbeb7dd21b4894f74d3feb44d69c49 Original-Change-Id: I8aafb0ef7d1b77cb8d386f4e73dc46ea3d8ee3a4 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-29intel/kunimitsu: do gpio configuration in coreboot instead of fsprobbie zhang
BUG=chrome-os-partner:44336 BRANCH=None TEST=Built and booted kunimitsu. Validation shows no regressions. CQ-DEPEND=CL:294757 Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295012 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11425 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-29intel/skylake: gpio macro adding - gpio output with term and 20k pdrobbie zhang
This is also required for kunimitsu fab3 gpio settings. BUG=None BRANCH=None TEST=Built and booted kunimitsu. Change-Id: I61d71fe4576cd57d17f21aecb188cd5b7fdecca0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: f65c2618a47c71aad277fb2a11b17ade0a97e5f8 Original-Change-Id: Iebf272b5cc3e67ec35259f5b3e9041ab4cdaa207 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294757 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Implement HW Sequence based WP status read functionalityBarnali Sarkar
Early(romstage) SPI write protected status read(wpsr) functionality was broken causing 2 sec timeout issue.Implementing HW Seq based rd status operation in romstage. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and tested using below command flashrom -p host --wp-enable [this should enable WP on flash chip] Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked) flashrom -p host --wp-disable [this should disable WP on flash chip] Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked) Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488 Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294445 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.Subrata
Created generic library to implement SPI read, write, erase and read status functionality for both ROMSTAGE and RAMSTAGE access. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and verify SPI read, write, erase success from ELOG. Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2 Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Commit-Queue: Subrata Banik <subrata.banik@intel.com> Reviewed-on: http://review.coreboot.org/11422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: add WP to gpio tableWenkai Du
This is needed to fix error in depthcharge: src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up for flag 3. BUG=chrome-os-partner:44214 TEST=Verify depthcharge prints EC ID on boot up BRANCH=None Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3 Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: configure gpio pads prior to SiliconInit()Aaron Durbin
Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11420 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: fix kepler probingAaron Durbin
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Export GPIO for EC_IN_RWDuncan Laurie
Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Fix RMT disable of saved training dataDuncan Laurie
The RMT flag that was attempting to disable saved training to force a full memory train was happening too late. In testing I was actually hitting a case where FSP was training every time but it was not because it was properly being told to. This moves the check of the RMT flag from devicetree to happen ealier, before it is actually consumed by romstage_common(). BUG=chrome-os-partner:40635 BRANCH=none TEST=do both power off+on and warm resets to ensure that FSP is doing a full memory train every time with RMT enabled. Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7 Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294177 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11417 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: mask off txstate before setting new gpio valueAaron Durbin
The previously driven TX state of the buffer was not being cleared before or'ing in the new value. Fix this oversight. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Also dumped assembly and saw the masking happen. Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294541 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11416 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-29intel/skylake: Clean up Serial IO DMA channelsArchana Patni
This patch removes FixedDMA channels carryover code from BDW as in SKL Integrated DMA is present for each serial io controller. BRANCH=None BUG=BUG=chrome-os-partner:40383 TEST=Build and Boot kunimitsu. Tested IDMA on UART. Change-Id: I66c869d310febcda430809d194b53a903a21fd99 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 833a1980329fb03cf487482e9276c076ede0a0fa Original-Change-Id: If6ce19cd8d60c727c8f2ffcd9bb232521df63f08 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293060 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11415 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Force full memory train if RMT is enabledDuncan Laurie
RMT is useless if the memory does not do a full training pass, and since FSP does not seem to handle that case itself have coreboot not pass in a valid set of saved training data so FSP will do a full memory train. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot twice on glados with p2 and RMT enabled and see it do a full memory train on each boot. Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6 Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294067 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29fsp raminit: Add romstage_params to soc_memory_init_paramsDuncan Laurie
The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11413 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/braswell: allow dirty cache line evictions for SMRAM to stickChiranjeevi Rapolu
The BUNIT controls the policy for read/write access to physical memory. For the SMRAM range the policy was not allowing dirty evictions to the SMRAM when the core causing the eviction was not in SMM mode. This could happen when the SMM handler dirtied a line and then RSM'd back into non-SMM mode. The cache line was dirtied while in SMM mode, but when that particular cache line was evicted it would be silently dropped. Fix this by allowing the BUNIT to honor writes to the SMRAM range while the evicting core is not in SMM mode. The core SMRR msr provides the mechanism for disallowing general access to the SMRAM region while it is not in SMM mode. BUG=chrome-os-partner:43091 BRANCH=None TEST=Run suspend_stress_test and ensure there is no hang SMI handler on suspend-path. Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2 Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f Original-Reviewed-on: https://chromium-review.googlesource.com/292890 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: http://review.coreboot.org/11412 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/braswell: Adding conditional statements to turn on/off DPTF WIFI and WWANPrince Agyeman
TEST=Builds and boot on Cyan verified by DPTF team BUG=None BRANCH=None Change-Id: I38ddf4a104eb3183d424b5df6b5eab9d406327ef Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 47cbf3893f7d5f1dfad73f57a71ade9382b0a06a Original-Change-Id: Ide4b3987bfa5e7ec60ee4f47d0663bb71f8330b9 Original-Signed-off-by: Prince Agyeman <prince.agyeman@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291063 Original-Commit-Queue: Prince Agyeman <popagy@gmail.com> Original-Tested-by: Prince Agyeman <popagy@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11411 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/braswell: remove CBFS_SIZE option in SoC directoryAaron Durbin
CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. BUG=chrome-os-partner:43419 BRANCH=None TEST=None Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175 Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289832 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11410 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/fsp1_1/hob.c: Refactor file to match coreboot coding styleAlexandru Gagniuc
Avoid ASSERT() when a better solution exists, avoid UPPERCASE types when C99 types exist, and use stdlib functions where possible. Change-Id: Ia40ec8ff34ec82994b687d517dc4b145fb58716c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29drivers/intel/fsp1_1: Don't compile GOP support in romstageAlexandru Gagniuc
We don't need the code in romstage, and it saves us a few #ifdefs. Change-Id: I26d867566f07c7d80890cd01bf055be7497130d3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29soc/intel/common/fsp_ramstage.c: Don't die when printing HOB infoAlexandru Gagniuc
It doesn't make sense to die() when printing information. In fact the die() are protected by DISPLAY_HOBS config option. This can get confusing, so replace die() calls with printk(). Also since these messages are designed to be informational, keep them at BIOS_INFO log level. Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11456 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29fsp1_1: remove duplicate mrc caching mechanismAaron Durbin
For some reason fsp 1.1 has a duplicate mechanism for saving mrc data as soc/intel/common. Defer to the common code as all the existing users were already using the common code. BUG=chrome-os-partner:44620 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I951d47deb85445a5f010d23dfd11abb0b6f65e5e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Original-Commit-Id: 2138b6ff1517c440d24f72a5f399bd6cb6097274 Original-Change-Id: I06609c1435b06b1365b1762f83cfcba532eb8c7a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295236 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11454 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 02:41:55 +0000