coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-09-16	mb/google/poppy: Set UPD CmdTriStateDis for Atlas	Caveh Jalali
2018-09-15	mb/lenovo: Add Lenovo W500 as clone of Lenovo T400	Paul Menzel
2018-09-15	sifive/hifive-unleashed: enable CBMEM support	Philipp Hug
2018-09-15	soc/sifive: move ram_resource to mainboard	Philipp Hug
2018-09-15	arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706	Richard Spiegel
2018-09-15	arch/riscv: Configure delegation only if S-mode is supported	Jonathan Neuschäfer
2018-09-15	pcengines/apu2: enable IOMMU for all apu2 variants	Piotr Król
2018-09-15	nb/amd/pi/00730F01: Add initial native IVRS support	Timothy Pearson
2018-09-15	nb/amd/pi/00730F01: Initialize IOMMU device	Kyösti Mälkki
2018-09-15	mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree	Arthur Heymans
2018-09-14	drivers/intel/gma: Do not rely on CBLV in OpRegion Mailbox3	Nico Huber
2018-09-14	arch/x86/acpigen: Fix comment in _ROM method generator	Jonathan Neuschäfer
2018-09-14	nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume	Nico Huber
2018-09-14	device/ddr3: Prevent overflow when adding SMBUS Table 17 entries	Nico Huber
2018-09-14	arch/riscv: Only execute on hart 0 for now	Philipp Hug
2018-09-14	soc/intel/denverton_ns: Enable common block PMC	Julien Viard de Galbert
2018-09-14	ec/lenovo/pmh7: support 9bit address space	Alexander Couzens
2018-09-14	soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation	Philipp Hug
2018-09-14	soc/sifive/fu540: Initialize SDRAM	Philipp Hug
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
2018-09-14	soc/sifive/fu540: create ram_resource with actual memory size	Philipp Hug
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	Philipp Hug
2018-09-14	mb/google/octopus: Query the EC for board version	Karthikeyan Ramasubramanian
2018-09-14	arch/riscv: add missing endian.h header to io.h	Philipp Hug
2018-09-14	mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phase	peichao.wang
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-13	soc/sifive/fu540: Get SDRAM controller out of reset	Philipp Hug
2018-09-13	soc/sifive/fu540: Update clock settings according SiFive bootloader	Philipp Hug
2018-09-13	uart/sifive: make divisor configurable	Philipp Hug
2018-09-13	src/mainboard//: Set Mini-ITX boards' category to "mini"	Angel Pons
2018-09-13	src/*/intel: introduce warning when building with no IFD	Angel Pons
2018-09-13	src/*/intel/: clarify Kconfig options regarding IFD	Stefan Tauner
2018-09-12	soc/sifive/fu540: Initialize PLL and clock	Philipp Hug
2018-09-12	mainboards: Add SMMSTORE region in chromeos configs	Patrick Georgi
2018-09-12	soc/amd/stoneyridge: Fix more GPIO functions	Jonathan Neuschäfer
2018-09-12	rammus: add SPD mapping for rammus and shyvana support	kane_chen
2018-09-11	amd/stoneyridge: Enable BERT table generation	Marshall Dawson
2018-09-11	amd/stoneyridge: Set BERT region size when no TSEG used	Marshall Dawson
2018-09-11	soc/intel/baytrail: Remove trailing space in log message	Paul Menzel
2018-09-11	src/device/dram: Fix typo	Elyes HAOUAS
2018-09-10	soc/sifive: fix compiler warning	Philipp Hug
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
2018-09-10	mb/google/poppy/variants/nami: Add SPD for two memory parts	Ren Kuo
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
2018-09-10	mainboard/google/poppy/variants/rammus: Enable DA7219	marxwang
2018-09-10	soc/intel/cannonlake: Correct number of root ports for CNL PCH H	Maulik V Vaghela
2018-09-10	riscv: update misaligned memory access exception handling	Xiang Wang
2018-09-10	soc/sifive/fu540: add CLINT support	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang