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2018-02-16soc/intel/skylake: Switch to common PCR ASLLijian Zhao
Using common PCR asl for skylake/kabylake platform. BUG=None TEST=None Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-16soc/intel/common: Add generic PCR aslLijian Zhao
Access to PCH Private Configuration Space Register can be addressed via SBERG_BAR, the method is generic across several generations of Intel SOC. BUG=None TEST=None Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-16soc/intel/cannonlake: Add missing GPIO pin definitionsLijian Zhao
Fill the missing GPIO pin definitions, includeing community 3. Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-16google/gru: Fix GPIO_WP pull and polarity for ScarletJulius Werner
Turns out the write-protect GPIO polarity for Scarlet is different than for Kevin/Gru, and nobody ever told us. Also, it must not be configured with an internal pull-up or we'll not read the correct value. This patch fixes both issues. BRANCH=scarlet BUG=b:73356326 TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the right value in all cases. Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/google/poppy/variant/nautilus: Enable and configure DPTFSeunghwan Kim
This change enables DPTF and configures the policy. DPTF parameters were provided by internal power team. BUG=b:67877437 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23731 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/intel/glkrvp: Add FPF_STATUS section in fmd fileHannah Williams
Read cse file was not getting cached and taking about 500ms on every boot. Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15cpu/x86/16bit/entry16.inc: Fix typo in commentPaul Menzel
Add the missing *r* of the possessive pronoun *your*. Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/23758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-02-15drivers/generic/adau7002/adau7002.c: Fix null pointer dereferenceRichard Spiegel
Procedures acpi_device_scope() and acpi_device_name() can under certain conditions return NULL. Check the return before using them. This fixes CID 1385944 BUG=b:73331544 TEST=Build kahlee. Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23760 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15soc/amd/common/block/s3/s3_resume.c: Check mrc_cache_get_current() returnRichard Spiegel
Procedure mrc_cache_get_current() returns -1 for error, 0 for pass. Do check the return in procedure get_s3nv_info. This fixes CID 1385943 BUG=b:73333332 TEST=Build kahlee Change-Id: I0f6a58380a38d13120e997dcd966423d3c2af091 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15mb/google/octopus: Add new boardHannah Williams
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15siemens/mc_bdx1: Show mainboard hardware version on consoleWerner Zeh
Show mainboard version in the console log so that one can easily see it. Change-Id: I33bae8b340fce13c0cbe525521828929038b069a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15siemens/mc_bdx1: Enable PCA9538 I/O expanderWerner Zeh
The I/O expander on the mc_bdx1 is used to get the hardware version of the mainboard. This patch enables the chip driver for the I/O expander. Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15drivers/i2c: Add chip driver for I/O expander PCA9538Werner Zeh
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C bus. Add a chip driver to support this chip. Beside the pure chip driver two interface functions are provided to read the state of the pins and write output values to the pins. As the slave address of this chip is hardware configurable the function pca9538_get_dev() is used to get the right slave address. This function needs to be implemented in mainboard code if one needs to use the interface functions to read and write I/O state. Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-14drivers/i2c/designware: Remove spurious word ("familuar")Jonathan Neuschäfer
Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver") Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23714 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-14drivers/adau7002: Fix include fileDaniel Kurtz
Add missing license and include guard and remove unneeded include. BUG=b:72121803 TEST=compiles Change-Id: Ic359ed262086596a98131669f8eecd531857187a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23721 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-14soc/amd/stoneyridge: Set up LAPICMarc Jones
LAPIC setup is required to set virtualwire mode for legacy interrupts. This was omitted when stoneyridge was changed to use the common mp_init. BUG=b:72351388 TEST=Verify keyboard now works in SeaBIOS Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-13mb/google/poppy: Fix the SPD for samsung_dimm_K4A8G165WBFurquan Shaikh
Original SPD provided by the vendor had bytes after 254 shifted by 16 bytes. This change fixes the SPD data based on the latest details received from the vendor. BUG=b:72749394 TEST=Verified that the device with this memory part boots to OS fine. Also, mosys is able to dump the right memory information. Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-13drivers/uart/pl011: Improve PL011 driverDavid Hendricks
This adds a struct for registers along with some bits from ATF to the generic PL011 driver. It also adds a naive implementation of uart_tx_flush() which was previously stubbed out. Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-12arm64: Add read64() and write64()David Hendricks
Change-Id: I89cf4b996405af616f54cf2d9fabd4e258352b03 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23036 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12armv8: Allow for ARMv8 extensions to be chosenDavid Hendricks
There are now a few architectural extensions available for ARMv8, some of which introduce instructions or other features that may be useful. This allows the user to select an extension implemented on their SoC which will set the -march option passed into the compiler. Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-12mainboard/google/zoombini/variants/meowth: enable touchscreenNick Vaccaro
BUG=b:69011806, b:72179988 BRANCH=master TEST=Verify touchscreen on meowth works with this change. Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12amd/stoneyridge: Add S3 support to POSTMarshall Dawson
Add/update the romstage and ramstage paths to check for S3 resume and call the appropriate AGESA functions. TEST=Suspend/Resume Kahlee with full S3 patch stack BUG=b:69614064 Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12soc/amd/common: Call AmdS3FinalRestoreMarshall Dawson
AMD support in coreboot has typically not used the AmdS3FinalRestore() Entry Point. Add a call to it immediately prior to resuming to the OS. BUG=b:69614064 TEST=Check console log for execution Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12soc/amd/common: Add S3 resume functions to wrapperMarshall Dawson
Add new functions that can execute InitRtb, InitResume, LateResume, and FinalResume. Note that the name AmdInitRtb supersedes the deprecated AmdS3Save. TEST=Suspend/Resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12vc/amd/00670F00: Introduce S3FinalRestore helperMarshall Dawson
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that coreboot has been missing. Add the helper function that can call into the blob to execute this. BUG=b:69614064 Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12soc/amd/common: Replace missing AmdReleaseStruct() callsMarshall Dawson
The AGESA spec states that "Failure to release a structure can cause undesired outcomes." Uncomment the one in AmdInitLate(). The function only dealocates the structure used for the AGESA entry point, and not the internal data used by coreboot. Release the structure in AmdInitEnv(). This appears to have been an omission years ago when duplicating agesawrapper.c for every mainboard was still common. BUG=b:70671742 TEST=Build and boot Kahlee, inspect console log Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22888 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12soc/amd/common: Add S3 supporting functionsMarshall Dawson
Add functions that the wrapper will call to get and save the S3 data. The wrapper requires two types of data saved: * Non-volatile: Information that is the minimum required for bringing the DRAM controller back online. This change uses the common mrc_cache driver to manage the storage * Volatile: May be stored in DRAM; information required to complete the system restoration process. TEST=Suspend/Resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12ec/chromeec: Fix battery ACPI mutex levelMatt DeVillier
Commit 07fe618 [chromeec: Add support for reading second battery info] added a mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-12google/snappy: enhance BigDaddy USB#2 2.0 strengthKevin Chiu
Fine tune 14" BigDaddy USB#2 2.0 strength: PERPORTPETXISET: 7 PERPORTTXISET: 1 IUSBTXEMPHASISEN: 3 PERPORTTXPEHALF: 0 this value could have USB#2 2.0 EA/function pass. BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23649 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11soc/intel/cannonlake: Add Pch iSCLK programmingLijian Zhao
In order to reduce BOM cost and board area for imaging solution, the sensor requires a 19.2/24MHz reference clock from PCH. In addition to that, having PCH to supply the sensor reference clock will prevent dependency on CPU power management and also avoid level shifter cost. Pch iSCLK is only required for CNP-LP with the camera sensor on the platform. BUG=None TEST=Boot up into OS and read back PCH iSCLK programming through iotools. Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23367 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11mb/google/fizz: Set SATA GPIOs in bootblockShelley Chen
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mb/google/poppy/variants/nautilus: set oem_id, oem_table_id fields of ↵Naveen Manohar
acpi_header_t This change makes the Nautilus platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:68686020 TEST=Build, booted nautilus board. Verified kernel reads new strings. Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/23648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mainboard/google/meowth: Enable ECT againLijian Zhao
Previously ECT was disabled in commit 22401, on D0 stepping system and FSP version 7.x.20.52, disabling ECT will cause memory training failure and the system is stuck at post code 00D5h. BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass memory training and boot up into OS. Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-10mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_tKaiyen Chang
This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23670 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10drivers/adau7002: Add driver for handling ADAU7002Daniel Kurtz
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from Analog Devices. On some boards they are a used to convert a PDM audio data stream from a DMIC to an I2S signal. Add a driver for populating ACPI table entries for this part. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10drivers/i2c/da7219: Allow GPIO based interruptDaniel Kurtz
Allow specifying the DA7219 interrupt pin as either an Interrupt or GpioInt. BUG=b:72121803 TEST=(with whole patch series) Grunt Kernel discovers DA7219 on i2c0 Change-Id: I2d26731bf4c0ad590dad2c5d26c252371f415f9a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10soc/amd/stoneyridge: Put outl arguments in correct orderMartin Roth
outl takes value then port. BUG=b:72130849 Test=None Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-09chromeec: Fix ACPI compile warningLijian Zhao
For system without secondary battery, current DSDT will report warning during build time. Add a conditional check to make sure only battery index 0 can return success. TEST=Build pass. Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-09drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driverSubrata Banik
As per FSP 2.0 specification and FSP SOC integration guide, its not expected that SMBIOS Memory Information GUID will be same for all platform. Hence fsp_find_smbios_memory_info() function inside common/driver code is not generic one. Removing this function and making use of fsp_find_extension_hob_by_guid() to find SMBIOS Memory Info GUID from platform code as needed. Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08soc/intel/cannonlake: Add support for EMMC DLL updateLijian Zhao
Add option to have customized DLL setting for EMMC interface to make EMMC able to run at HS400 speed. BUG=None Change-Id: I38bc022d8c05dd1fbd03dc26aa6f33cd249e8248 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08mb/intel/kblrvp: Enable Kabylake RVP8V Sowmya
Add support for KBL RVP8 board * Add KBL RVP8 support in Konfig. * Add KBL RVP8 config option in make menuconfig. * Add descriptor and ME binary paths for RVP8 in Kconfig. * Add RVP8 board name Kconfig.name. * Add devicetree.cb for RVP8 in the variants path. * Add gpio.h for RVP8 in variants/include/variant path. TEST= Build and boot RVP8. Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23383 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-08mb/google/poppy/variants/nami: Revise AC/DC loadlinesGaggery Tsai
This patch revises AC/DC loadlines from VRTT reports. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 b:72129954 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-08soc/intel/skylake: Clean up SMBIOS Table Type 17 creationSubrata Banik
* Add Memory Channel Status Enum for Channel detection. * Align > 80 characters per line. * Add hob_size == 0 check. Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17Subrata Banik
This patch ensures to have Type 17 SMBIOS table for CannonLake Platform. TEST=Enable to get correct SMBIOS DIMM type information as per SMBIOS spec 3.1 Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/google/fizz: Set Pmax to 120 for all SKUsShelley Chen
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4 (71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) + ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W. BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23633 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 18:52:18 +0000