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2007-09-19Add support for a precompressed LZMA payload (trivial).Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19Sorry, I mixed up two patches. Reverting this change.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19Add support for a precompressed LZMA payload (trivial).Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.Yinghai Lu
For example: in C51/MCP55 or C51/MCP51 Will allow 1. C51 at 0x10 to 0x14, and MCP at 0 to 4 2. C51 at 1 to 4, and MCP at 7 to 0x0a The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it needed), and will prevent us from putting them on bus 0. Typical values for c51/mcp55 or c51/mcp51: HT_CHAIN_UNITID_BASE = 0x10 # for C51 HT_CHAIN_END_UNITID_BASE = 0 # for mcp If only have mcp with c51, HT_CHAIN_UNITID_BASE = 0 # for MCP #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20 Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14This is a full rewrite of all the CS5530/CS5530A code. The previous code wasUwe Hermann
mostly undocumented, had a broken coding style, contained lots of dead code and had several other problems, e.g. it enabled write access to the ROM (why?), it unconditionally enabled primary/secondary IDE (which should have a config option) and that even _twice_ (which is um... wrong). The new code - has 'ide0_enable' and 'ide1_enable' config options (which actually work) to enable/disable the primary/secondary IDE interface in Config.lb. - Does _not_ enable write access to the ROM (or is there some good reason to do that? If so, it should at least have a config option). - Contains a bit more documentation. - Uses readable (and documented) #defines instead of hardcoded magic values. - aaand... it actually compiles ;-) Yep, that's right. The previous code wouldn't even build, as it hadn't been fully ported from v1 (still used v1 functions which are simply not available in v2). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13I still don't understand a word, but I tried to improve the documentation. ↵Stefan Reinauer
(trivial) Please fix this if you can. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13Fix abuild run of the MSI MS-6178 (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13Add a common/global failover.c file which can be used by allUwe Hermann
(or at least most) mainboards. This should put and end to copy-paste'ing the same file again and again for every mainboard. Fix the build for the MSI MS-6178 target (wrong location of the common failover.c file). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-12Add initial support for the Intel 810 based board MSI MS-6178.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Partial changes and fixup.Ronald G. Minnich
Removed reset.c and added copyright headers. Remove debug.c. It is not used and should not be here. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08Welcome to PC Engines and the ALIX 1C!Ronald G. Minnich
This is a geode LX board. There are timing settings that are not right yet, we are still trying to get our board to boot Linux :-) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Athlon64 x2 5000+ CPU.Torsten Duwe
A trivial one-liner for the CPU I happen to have. The sales docs said it's a "G1 revision", but the Rev F code works just fine. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12Fix Agami Aruma target (the only one using the part)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12trivial: clarify comment on ADM1026_DEVICE addressPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12some agami i2c mergesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12[Arg! Forgot to 'svn add', sorry]Uwe Hermann
Generic driver for pretty much all known Standard Microsystems Corporation (SMSC) Super I/O chips. Most of the SMSC Super I/O chips seem to be similar enough (for our purposes) so that we can handle them with a unified driver. So far only the ASUS A8000 has been tested on real hardware! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12Generic driver for pretty much all known Standard Microsystems CorporationUwe Hermann
(SMSC) Super I/O chips. Most of the SMSC Super I/O chips seem to be similar enough (for our purposes) so that we can handle them with a unified driver. So far only the ASUS A8000 has been tested on real hardware! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-20Artec Group dbe61 mainboard support.Marc Jones
Now uses CAR. New code for SPD-less memory implementation. Updated IRQ routing. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19Various minor cosmetics and coding style fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19The GPIOs used for UART2 RX and TX were reversed.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19This patch fixes up a couple mistakes I made with the i82810 and mew-vw to makeCorey Osgood
the system boot to a command line. This patch comments out the code to set up the vga framebuffer to allow the system to boot, without this fix the system hangs during elfboot. The only line that is absolutely necessary to change is the SMRAM setup, however I've commented out all vga setup to make it very obvious to both the kernel/payload and anyone looking at the code that vga isn't currently working. This setup might also be better handled in northbridge.c, if it doesn't need to be done before ram init, yet another reason to comment it all. In the future, LinuxBIOS needs to be told that the graphics memory area, 1mb or 512kb (at the user or developer's option), is reserved for the onchip vga, but I'm not sure if it's taken at the top or bottom of the memory, yet. LB may also need to set a base address for the AGP aperture and/or be told that range is reserved as well, whether this was originally the job of the system bios or vga bios is still a mystery. It also corrects the number of entries in irq_tables.c, without this fix the kernel would probably complain and hang due to unmapped IRQs. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14small agami aruma configuration updates (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Fix the static device tree of the ASI MB-5BLMP target. This was broken inUwe Hermann
more than just one way. This version should be (more) correct. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting ↵Marc Jones
should only shift the mask one bit, not two. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Small bugfix in i82801xx_lpc.c.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Add initial support for the Intel 82810 northbridge.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14This patch adds support for the Intel i82810 northbridge and various i82801xxCorey Osgood
southbridges, along with the Asus MEW-VM. With this, my machine attempts to boot linux, but does so very slowly and fails during the boot process, probably because of the irq tables. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-12Add the AMD DB800 (AKA Salsa) mainboard.Marc Jones
The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07Minor tweaks in the 440BX RAM init code (trivial).Uwe Hermann
Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards.Nikolay Petukhov
Both are very similar, thus both use the JUKI-511P target. Linux with patches from Juergen Beisert (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html) boots and work fine (ide, usb, ethernet, serial, keyboard and sound work normally). Problems: - Filo loads a bzImage only from ide0 (ide1 doesn't work yet). - Video doesn't work, yet. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-06Add support for the Winbond W83977F-A Super I/O.Nikolay Petukhov
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Tyan S1846: Minor fixes in static device tree (trivial):Uwe Hermann
- Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse in the output of 'lspnp -v'. - The floppy on 2e.f was a typo, should have been 2e.e from the beginning. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Fix the static device tree of the Tyan S1846. Especially theUwe Hermann
Super I/O part was incorrect. Also, add ide0_enable/ide1_enable variables, and enable both the primary and secondary IDE interface per default. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Intel 82371EB: Some code simplifications (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-02The UART disable code was causing a hang and was worked around with aMarc Jones
return that skipped the disable code. This patch removes the return and fixes the UART disable code. The problem was that the disable code was ORing bits into the Legacy_IO MSR causing issues with the LPC SIOs init code that would manifest as a hang because the IO would not be decoded correctly. ANDing to clear the bits fixes the issue. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Drop duplicate 82371AB device IDs (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Use the common LinuxBIOS license header format.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Intel 82371EB: Add IDE init support.Uwe Hermann
In a mainboard's Config.lb file you can configure whether the primary and/or secondary IDE interfaces shall be enabled. Also, various fixups in the rest of the southbridge code, most notably the early SMBus code, plus some documentation improvements. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-28Lower the RAM init delays we use on the Intel 440BX.Uwe Hermann
As per JEDEC, we should wait 200us until voltages and clocks are stable. Then apply NOPs for 200 clock cycles (for simplicity we use 200us here). All other delays are so low that we get away with just waiting 1us. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Various 440BX and Tyan S1846 related minor changes and fixes (trivial):Uwe Hermann
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's available on all boards, regardless of what DIMMs you use. Tested on the Tyan S1846, works fine. - Properly set the PAM registers to allow the region from 768 KB - 1 MB to be used as normal RAM (required for the above). - Document all of this properly. Add/improve other documentation, too. - Simplify and document code in northbridge.c. - Cosmetics and coding style. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Init for the Intel 82371EB southbridge: make all ROM/BIOS regionsUwe Hermann
accessible (but not writable), so that reading/loading a payload from that area can work (for instance). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-26This patch fixes the processor name string for Rev F. CPUs.Sven Kapferer
It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c. The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Add initial support for the ASUS A8N-E board.Philipp Degler
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Drop the src/southbridge/amd/cs5536_lx directory and its contents, asUwe Hermann
the new src/southbridge/amd/cs5536 code completely replaces it. The Artecgroup dbe61 board currently uses it, but that is broken anyway at the moment. A fix to use the new CS5536 code for it is being worked on. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Various IT8712F fixes:Philipp Degler
- Add missing IT8712F_GPIO definition. - Add functions for entering and exiting MB PnP mode. - Add some more device init lines to pnp_dev_info[]. Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Small patch that adds an error message in case the keyboard selftest fails.Philipp Degler
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22reverting 2683, NAK by YhLu, patch not necessary.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22Add missing license headers, minor cosmetic fixes in existing headers.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Drop the (non-working, almost non-existant) support forUwe Hermann
- the Transmeta TM5800 northbridge - the Densitron DPX114 mainboard (the only one using the TM5800) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Drop romcc related stuff, as this board only uses CAR.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 17:33:50 +0000