summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02intel/{skylake,apollolake}: Enable signalling of error conditionPatrick Georgi
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more instances. Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1357450, #1357449 Reviewed-on: https://review.coreboot.org/17054 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panelsJulius Werner
Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/17108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-01google/eve: Add new boardDuncan Laurie
Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-01soc/apollolake: Add soc core initRavi Sarawadi
Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-31ec/acpi: Add missing includeNico Huber
Change-Id: I61c2191f28b6c2c9a6bc587dc3b6c2ae28205192 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-31lib/program.ld: add .sdata sectionsAaron Durbin
Ron reported some toolchain emitting .sdata sections. Let's ensure we catch objects in those sections instead of getting dropped on the floor for architectures which emit those sections. Change-Id: I0680228f8424f99611914ef5fc31adf5d3891eee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-29Add option to build Ada debugging codeNico Huber
Ada knows a pragma `Debug` that is used to exclude procedure calls from a release build. The new option `DEBUG_ADA_CODE` enables those procedure calls. Change-Id: Id5298e5819606c3d1cf2a2a1cd4f1d5d1227aa4f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-29nb/intel/sandybridge/gma: Always initialize DP buffer translationNico Huber
These settings should be always made by the firmware, no matter if we set up graphics or not. It looks like Linux doesn't even know these registers. The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1, 2]. They match the settings that were done in the native graphics path for Ivy Bridge. I expect the differences to be an update (i.e. the set- tings we did on the Sandy Bridge path were just outdated). Also, these settings affect the PCH and not the CPU which are independent from each other. [1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 3: PCH Display Registers (SandyBridge) Doc Ref #: IHD-OS-V3 Pt3 – 05 11 https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf [2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 4: South Display Engine Registers (Ivy Bridge) Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17073 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-29soc/intel/common: Add reset.c to postcarFurquan Shaikh
ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-29nb/intel/i945/gma.c: Homogenize code for PCI IDs.Elyes HAOUAS
Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17174 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-28riscv: add the lowrisc/nexys4ddr mainboardRonald G. Minnich
This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17132 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-28lars/kunimitsu: Add other sensor in _ART for fan controlSumeet Pawnikar
This patch updates the _ART table with other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. Also, updates the temperature values in DPTF policy for better performance. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified this updated _ART table on these boards with different workloads. Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332349 Reviewed-on: https://review.coreboot.org/17066 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-28mainboard/google/reef: allow variants to override NHLT OEM stringsAaron Durbin
In certain cases a board variant may need to override the NHLT OEM strings in the main NHLT table. Therefore, provide that path. BUG=chrome-os-partner:56918 Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17167 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2016-10-28mainboard/google/reef: update comment for DMIC config usageAaron Durbin
Going forward GPIO_17 is used to determine the configuration of the board w.r.t. the number of DMICs on the board. BUG=chrome-os-partner:56918 Change-Id: I03edb880e0649977030c1b87219ebebac631a519 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17163 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-28soc/intel/skylake: don't hardcode GPE0 standard regAaron Durbin
While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-28skylake: Add GPIO macro for configuring inverted APIC inputDuncan Laurie
Add a GPIO macro that allows a pin to be routed to the APIC with the input inverted. This allows a normal interrupt to get used as a GPE during firmware and still be used as a perhiperal interrupt in the kernel. BUG=chrome-os-partner:58666 TEST=boot en eve and use TPM IRQ in firmware and OS Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17176 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28soc/intel/skylake: put back uart_debug.c into verstageAaron Durbin
uart_debug.c was accidentally dropped in verstage in 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (https://review.coreboot.org/17136). Fix that. Change-Id: If37a028550d419bada80d157c4de02fd82d26c89 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17175 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-28pcengines/apu1: Add RS485 configurationKyösti Mälkki
In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-10-27soc/intel/skylake: make inline function staticNaresh G Solanki
Make bootblock_fsp_temp_ram_init as static inline. Change-Id: Iacf24728a45fc6554d7a425feecc25e55ac5da6c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-27driver/intel/fsp2_0: Reset on invalid stage cache.Naresh G Solanki
Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is invalid during S3 resume. Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27mainboard/google/reef: drop disabling periodic training for micronAaron Durbin
In anticipation of getting fixed material remove the disabling of periodic training for MT53B512M32D2NP and MT53B256M32D1NP. BUG=chrome-os-partner:59003 Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17130 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27mainboard/google/reef: clarify memory part number detailsAaron Durbin
Explain the reasoning for the part_num strings used in the memory SKU table explaining the necessity of keeping mosys in sync with the strings used. It's possible that actual part numbers could change as the higher speed material gets cheaper, for example. BUG=chrome-os-partner:58966 Change-Id: If895e52791dc56e283261b3438106116b8b2ea05 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17129 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Add support for eSPI SMI eventsDuncan Laurie
Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17134 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Prepare GPE for use in bootblockDuncan Laurie
Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27skylake: Support for early I2C TPM driverDuncan Laurie
Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17136 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Fix wake source reporting with Deep S3Duncan Laurie
The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Use COMMON_FADTDuncan Laurie
Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26google/reef/variants/pyro: Use WCOM Touchscreen driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17092 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-26nb/x4x/gma.c: Remove writes to DP, FDI registersArthur Heymans
Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17111 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26nb/gm45/gma.c: Remove writes to DP, FDI registersArthur Heymans
Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17110 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26nb/intel/i945: Add PCI id for I945GCNico Huber
Also drop an odd comment about the resource allocator which seems to work fine, with the right id. Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17095 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26intel/skylake: Add support to enable wake-on-usb attach/detachFurquan Shaikh
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-26soc/intel/apollolake: Enable write-protect SPI flash range supportFurquan Shaikh
Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26soc/intel/skylake: Use intel common support to write-protect SPI flashFurquan Shaikh
BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26soc/intel/common: Enable support to write protect SPI flash rangeFurquan Shaikh
Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-25riscv: add the lowrisc System On Chip supportRonald G. Minnich
Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17119 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-25mb/ga-g41m-es2l: remove unneeded IGD IRQ setting in ACPIArthur Heymans
According to: "Intel ® 4 Series Chipset Family datasheet" the IGD only has 1 IRQ pin. Change-Id: I974f002f5a213056f4593a1eab10772527bb241d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17098 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25nb/i945/gma.c: Set the MSAC register correctlyArthur Heymans
This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17094 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-10-25mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3Naresh G Solanki
Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25Revert "soc/apollolake: Add soc core init"Aaron Durbin
This reverts commit a52f883b100f3229dd4d86c81c08781993861f73 (https://review.coreboot.org/16587). The above commit caused another sever kernel boot regression upwards of 2 minutes to get through kernel init on quad core systems. BUG=chrome-os-partner:58994 Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17121 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-25google/oak: Add derivative board HanaYidi Lin
CQ-DEPEND=CL:379684 BUG=chrome-os-partner:58064 TEST=verified on hana rev0 Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8 Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/379504 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25rockchip/rk3399: gru/kevin: drop unused sdram configsLin Huang
There are some sdram configurations that are no longer used. Drop them. BUG=None BRANCH=None TEST=None Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399122 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25rockchip/rk3399: reset system if DDR init failsLin Huang
We found sdram may fail in pctl_cfg(), so we check the status in this function. If it exceeds 100ms still in this function, we will restart the system. We also found there are rare chances DDR training fails, so also restart system in that case. BUG=chrome-os-partner:57988 BRANCH=None TEST=coreboot resets on failure and eventually the system comes up Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11 Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/397439 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17045 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25mb/emulation: Select QEMU-i440fx by defaultJonathan Neuschäfer
It's a better default than QEMU-armv7, which is currently the default board when coreboot is configured for the first time, because most coreboot development targets x86. With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU become: git clone https://review.coreboot.org/coreboot.git && cd coreboot make crossgcc-x86 make olddefconfig && make qemu-system-x86_64 -bios build/coreboot.rom Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16987 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-25arch/x86/acpigen_dsm: Add support for DSM typesFurquan Shaikh
Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25arch/x86/acpigen: Add support for _DSM method generationFurquan Shaikh
Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17090 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25drivers/i2c/generic: Re-factor SSDT generation codeFurquan Shaikh
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17089 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 05:54:27 +0000