summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-07-06PCI: Use PCI_DEVFN macro instead of DEV_FUNCWerner Zeh
There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-05siemens/mc_bdx1: Set up MAC address for available i210 MACsWerner Zeh
Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-02soc/apollolake: Allow enable/disable of LPSS S0ix from devicetreeSaurabh Satija
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Add GPE routing codeShaunak Saha
This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not neededAndrey Petrov
On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15494 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02google/reef: Add DA7219 support in acpiSathyanarayana Nujella
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add Audio DSP deviceHarsha Priya
Add the Audio DSP device for apollolake as a PCI driver with a static scan_bus handler so generic devices can be declared under it. This is for devices like the Maxim 98357A which is connected on the I2S bus for data but has no control channel bus and instead just has a GPIO for channel selection and power down control and needs to describe that GPIO connection to the OS via ACPI. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/15528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: handle p2sb quirksAaron Durbin
The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-02amd/olivehillplus: Fix PCIe lane number comments.Derek Waldner
Correct the GPP PCIe lane number comments so that they match the code. Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25 Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com> Reviewed-on: https://review.coreboot.org/15095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
Have the different acpi_device_ path functions use a different static buffer so they can be called interchangeably. Change-Id: I270a80f66880861d5847bd586a16a73f8f1e2511 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02soc/intel/skylake: Add function for gpio_t to ACPI pin translationDuncan Laurie
Add the function defined in gpio.h to translate a gpio_t into a value for use in an ACPI GPIO pin table. For skylake this just returns the gpio_t value as the pins are translated directly and they are all in the same ACPI device. Change-Id: I00fad1cafec2f2d63dce9f7779063be0532649c7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15520 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02drivers/generic/max98357a: Fix naming and ACPI path handlingDuncan Laurie
The upstream kernel driver is not using the of-style naming for sdmode-gpio so remove the maxim prefix, and remove the duplicate entry for the sdmode-delay value as well. Also fix the usage of the path variable, since the device path uses a static variable it can't be assigned that early or it will be overwritten by later calls. This results in the following output for the _DSD when tested on reef mainboard: Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x02) { Package (0x02) { "sdmode-gpio", Package (0x04) { \_SB.PCI0.HDAS.MAXM, Zero, Zero, Zero } }, Package (0x02) { "sdmode-delay", Zero } } }) Change-Id: Iab33182a5f64c89151966f5e79f4f7c30840c46f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15514 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate gpio_t into ACPI pinDuncan Laurie
There are four GPIO communities in this SOC and they are implemented as separate ACPI devices. This means the pin number that is used in an ACPI GPIO declaration needs to be relative to the community that the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig so this function actually gets used. This was tested on the reef mainboard by verifying the output of the SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed as pin 0x24 which is the value relative to the Northwest community. Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
Add a function for an SOC to define that will allow it to map the SOC-specific gpio_t value into an appropriate ACPI pin. The exact behavior depends on the GPIO implementation in the SOC, but it can be used to provide a pin number that is relative to the community or bank that a GPIO resides in. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659bcf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15512 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02google/reef: ACPI: Move touchpad to SSDT and remove TPMDuncan Laurie
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add support for LPSS I2C driverDuncan Laurie
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate device into ACPI nameDuncan Laurie
Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01lib: remove ulzma()Aaron Durbin
That function is no longer used. All users have been updated to use the ulzman() function which specifies lengths for the input and output buffers. Change-Id: Ie630172be914a88ace010ec3ff4ff97da414cb5e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15526 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-01Kconfig: Show DEBUG_BOOT_STATE in the Debug menuJonathan Neuschäfer
Change-Id: I22441ee0d19aa1b2e2f40278ce30092c86e0adc9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15522 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01AGESA boards: Fix split to romstage and ramstageKyösti Mälkki
Boards broken with commit: 062ef1c AGESA boards: Split dispatcher to romstage and ramstage Boot failure with asus/f2a85-m witnessed around MemMS3Save() call, message "Save memory S3 data in heap" in verbose agesa logs was replaced by a system reset. Default stubs for MemS3ResumeConstructNBBlock() returned TRUE without initializing the block contents. This would not work for case with multiple NB support built into same firmware. MemMCreateS3NbBlock() then returned with S3NBPtr!=NULL with uninitialized data and MemMContextSave() referenced those as invalid pointers. There is no reason to prevent booting in the case S3 resume data is not passed to ramstage, so remove the ASSERT(). It only affects builds with IDSOPT_IDS_ENABLED=TRUE anyways. Change-Id: I8fd1e308ceab2b6f4b4c90f0f712934c2918d92d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-07-01skylake: Generate ACPI timing values for I2C devicesDuncan Laurie
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO linesAbhay Kumar
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15447 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-01mainboard/google/reef: Use common NHLTSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports. Reef supports two audio codecs, Dialog 7219 for headsets and Maxim 98357 for speakers. Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/intel/amenia: add NHLT supportSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports as well select the hardware used on the board. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15024 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01soc/intel/apollolake: add initial NHLT supportSaurabh Satija
Provide the initial NHLT support for the following hardware: 1. 2 channel digital microphone array 2. Dialog 7219 headset 3. Maxim 98357 speaker amplifiers. The code utilizes the Intel SoC common NHLT support. Change-Id: Ic31e834a08f29c66512a7a63ad7bb35e0374e86a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15504 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-01soc/intel/common: use nvs.h include for nhlt codeAaron Durbin
The nvs.h header is the one which defines global_nvs_t proper. Don't rely on an indirect inclusion. Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15503 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-01soc/intel/apollolake: typedef global_nvs_t for consistencyAaron Durbin
Every other platform has global_nvs_t as a typedef. For some reason apollolake didn't bother following current conventions. Fix this omission to allow for better code sharing and consistency. Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15502 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-30vbnv: Do not initialize vbnv_copy in vbnv layerFurquan Shaikh
If read_vbnv finds that the vbnv_copy is not valid, it initializes it with the correct HEADER_SIGNATURE and other attributes. However, the vbnv copy is checked for validity and initialized at the vboot layer as well. Since, vboot is the owner of this data, it should be the one initializing it. Thus, if read_vbnv sees that the data is not valid, simply reset it to all 0s and let vboot layer take care of it. This also removes the need for additional checks to ensure that the dirty vbnv copy is properly updated on storage. Change-Id: I6101ac41f31f720a6e357c9c56e571d62e0f2f47 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15498 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-30soc/apollolake: Expose a function to read pmc barShaunak Saha
This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-30fsp_broadwell_de: Enable Super I/O address range decodeWerner Zeh
If there is an external 16550 like UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Tested-on: Siemens MC_BDX1 Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15495 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-30vendorcode/siemens: Add extended info block support to hwilibWerner Zeh
Add support for a fourth info block type to hwilib. This block provides new values and is now variable in length. Change-Id: Ia928b4a98b806ba3e80fb576b78f60bb8f2ea3fc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-30soc/intel/apollolake: fix space indention in pm.hAaron Durbin
More spaces missed in review. Change-Id: I842da05ca6ad4f2c13d2d42433e41da57ccf7f96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15500 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/{common,skylake}: provide common NHLT SoC supportAaron Durbin
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29lib/nhlt: drop nhlt_soc_add_endpoint()Aaron Durbin
The nhlt_soc_add_endpoint() is no longer used. Drop its declaration. Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15489 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-29soc/intel/skylake: refactor nhlt supportAaron Durbin
Utilize the new NHLT helper functions by driving the NHLT endpoints through data descriptors. Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15488 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-29soc/intel/skylake: fix nhlt/ssm4567.c indentionAaron Durbin
Whitespace fix for improper space usage for indention. Change-Id: Ia6470bf152c57786d2d7f3d35bbf0609a2ee3ba2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15487 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29lib/nhlt: add helper functions for adding endpointsAaron Durbin
In order to ease the porting of supporting NHLT endpoints introduce a nhlt_endpoint_descriptor structure as well as corresponding helper functions. Change-Id: I68edaf681b4e60502f6ddbbd04de21d8aa072296 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/apollolake: Change PCI macros to match SkylakeAndrey Petrov
Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-29soc/intel/apollolake: Update Upd header files for FSP Label 143_10Brandon Breitenstein
New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15459 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29vbnv: Do not silently reset cache in read_vbnvFurquan Shaikh
Currently, read_vbnv performs a reset of the vbnv cache if it is not valid. However, this information is not passed up to the vboot layer, thus resulting in missed write-back of vbnv cache to storage if vboot does not update the cache itself. Update read_vbnv to return a value depending upon whether it wants a write-back to be performed when save is called. Return value: 0 = No write-back required 1 = Write-back of VBNV cache is required. Change-Id: I239939d5f9731d89a9d53fe662321b93fc1ab113 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29AMD k8 fam10: Refactor S3 recoveryKyösti Mälkki
Change-Id: I09c218ca05391e8d80880be0aa5bdfd5079acf85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki
Platform is with RELOCATABLE_RAMSTAGE so nothing to backup. Change-Id: I2397db8affb084e34ca89dac4840f966b994e636 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMDFreddy Paul
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines. Without this SDCARD will throw data read/write errors. BUG=chrome-os-partner:54676 TEST=Build and boot to OS. Verify SD card is detected and data read/write works well. Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15345 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28soc/intel/apollolake: Add NHLT table region to ACPI global nvsSaurabh Satija
Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-28apollolake: Add ACPI device for audio controllerSaurabh Satija
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15026 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28intel/amenia: Configure unused PadsJagadish Krishnamoorthy
Configure unused Pads as NC and sort the pads according to the gpio community. Move the pad configurations from mainboard to gpio.h BUG=none TEST=Boot to OS and check all functionalities. Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15327 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 18:19:39 +0000