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2018-12-19soc/intel/cannonlake: SATA and DMI power optimizeLijian Zhao
Expose the FSP interface to enable SATA and PCH side DMI power optimize options. Actual step executed in FSP, step defined in cannonlake pch BIOS spec(CDI# 570374). Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 Reviewed-on: https://review.coreboot.org/c/30211 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19soc/intel/skylake: Add Sagv enum value definitionPraveen hodagatta pranesh
SaGv(system Agent Dynamic Frequency) have 4 settings Disabled, Fixedlow, Fixedhigh, Enabled. This patch add all 4 settings in enum definition and used in devicetree. BUG=None Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95 Reviewed-on: https://review.coreboot.org/c/30305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc/intel/braswell/linclude/soc/device_nvs.h: Fix typoFrans Hendriks
Use 'BAR 1' for the bar1 structure fields. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-12-19mb/google/kahlee: Remove board_id check for Liara 2T timingsMartin Roth
Use 2T memory timings on Liara for all board IDs. BUG=b:116082728 TEST=Build & boot on Liara Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-12-19mb/google/variant/nocturne: set CONFIG_NO_FADT_8042Nick Vaccaro
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller. This speeds up boot on nocturne by 1.3 seconds: Before change: [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem After change: [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem BUG=b:120960844 BRANCH=none TEST=build, flash, and boot nocturne; check dmesg to verify that boot is faster and that you don't see the following log in dmesg: [0.671501] i8042: Probing ports directly. Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/30283 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19google/rambi: disable TXE in devicetree for all variantsMatt DeVillier
The TXE PCI device serves no function under Linux, and doesn't work properly under Windows, so disable/hide it from the OS. Test: Boot Windows 10 on google/squawks, verify TXE not visible under Device Manager. Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19google/cyan: set touchscreen GPIO to non_maskableMatt DeVillier
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This not only broke the touchpad functionality, but caused issues with the touchpad as well. Revert the touchpad to being non_maskable for all cyan variants with a touchscreen. Test: boot GalliumOS on google/cyan with a range of kernel versions (4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional, touchpad working properly (not jittery) Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19mb/asus/maximus_iv_gene-z: Select NO_UART_ON_SUPERIOTristan Corrick
This board doesn't have a UART on the super I/O. Selecting this option speeds up boot time from ~493 ms to ~416 ms. Change-Id: I1d84f373831381da79022638e1082adf68f47aad Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer
Quoting from the RISC-V Privileged Architecture manual version 1.10, chapter 3.1.11: The FS and XS fields use the same status encoding as shown in Table 3.3, with the four possible status values being Off, Initial, Clean, and Dirty. Status FS Meaning XS Meaning 0 Off All off 1 Initial None dirty of clean, some on 2 Clean None dirty, some clean 3 Dirty Some dirty Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28987 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mb/sifive/hifive-unleashed: remove the definition of MAX_CPUSXiang Wang
When I debug with HiFive Unleashed, I found that hart 4 could not be running. Then find the duplicate MAX_CPUS definition. The correct MAX_CPUS is located in src/soc/sifive/fu540/Kconfig Change-Id: I583f6ba548daeeb6c7e341dc3fa8817e7dec5697 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/30179 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer
Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-19smsc/sch5147: Implement ACPI handling of a few LDNArthur Heymans
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19mb/lenovo/thinkcentre_a58: Add mainboardArthur Heymans
The following was tested: - Using two DDR2 DIMMs - S3 sleep and resume (on SeaBIOS it needs sercon disabled) - Ethernet NIC - Libgfxinit (native res and textmode) - SATA - USB - 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz) - PS2 Keyboard - Serial output TODO: - Add ACPI code for SuperIO devices (done in a follow-up patch) - Add documentation TESTED with SeaBIOS (sercon disabled), Linux 4.19 Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19superio/smsc: Add SCH5147Arthur Heymans
There are no public datasheets for this SuperIO. The results are from probing the registers manually. Change-Id: Ie5659533c5f224603f918d17942a7057e6701222 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19mb/foxconn/g41s-k: Don't reprogram inherited subsystemidArthur Heymans
Change-Id: I85b5aef758a1ed30c46ed0adabec3293edb0f3fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19soc/intel/skylake: Generate DMAR tables for FSP 1.1 boardsMatt DeVillier
Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table] only generates DMAR tables for boards using FSP 2.0, which leaves out Skylake Chromebooks, which use FSP 1.1. Correct this omission by adding the same functionality for FSP 1.1 boards. Test: build/boot on U-series Skylake Chromebook, observe IOMMU fully functional with intel_iommu=on kernel parameter. Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-19soc/intel/cannonlake: Auto turn on HDA controllerLijian Zhao
Update HDAenable bit in Fsp memory init UPD data base on devicetree settings. BUG=N/A TEST=N/A Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Use meaningful SATA modeLijian Zhao
Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19soc/intel/cannonlake: Declare SATA Mode clearLijian Zhao
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it more clear in header file. Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19soc/intel/cannonlake: Enable CPU flexible ratioLijian Zhao
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been set to zero. BUG=N/A TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is changing. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82 Reviewed-on: https://review.coreboot.org/c/30216 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mb/asrock/h81m-hds: Allow "keep state" for power_on_after_failTristan Corrick
When I added the cmos.layout file, I did not realise that the southbridge code cleverly emulated the "keep state" option. Tested on an ASRock H81M-HDS. The `Keep` option works as it should. Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-19sb/intel/lynxpoint: Don't force state keep after power failTristan Corrick
The deleted line crept in with commit 562db3bb3fa1 ("libpayload: find source of input characters"). Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable` via CMOS. After this patch, the system no longer powers on as soon as power is restored after a power failure. Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservationFrans Hendriks
RAM is reserved for Chromeos even when Chrome is not used. Use CONFIG_CHROMEOS to determine if RAM must be reserved. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19mb/google/sarien: Enable ELAN Touchpad and Disable ALPS TouchpadChris Zhou
Enable ELAN Touchpad and Disable ALPS Touchpad BUG=b:119628524 BRANCH=master TEST=ELAN Touchpad can work normally. Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-19soc/intel/cannonlake: Amend comment typoLijian Zhao
Fix typo of "VGOIO" back to "VGPIO". Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ia2b7cb0e5fe2817acc3e3f4656b98dc2462b397f Reviewed-on: https://review.coreboot.org/c/30147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-19mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19{device,drivers}: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ib96bf7d48711f518e36f8d12244b5749d84a0f68 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19cpu: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ica9514609616e0602fae9b0437d3fa404b645878 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Idef8c556ac8c05c5e2047a38629422544392cd62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc/intel/cannonlake: Add Acoustic featuresLijian Zhao
Expose the following FSP UPD interface into coreboot, which is the following: AcousticNoiseMitigation FastPkgCRampDisableIa FastPkgCRampDisableGt FastPkgCRampDisableSa FastPkgCRampDisableFivr SlowSlewRateForIa SlowSlewRateForGt SlowSlewRateForSa SlowSlewRateForFivr Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10 Reviewed-on: https://review.coreboot.org/c/30207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19lib/fit: Normalize spaces in board names to dashesJonathan Neuschäfer
CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces inside compat strings aren't nice, so let's convert all spaces to dashes. Change-Id: I46f2b2d7091782e04df5476e50698001511f664b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-19mb/google/octopus/var/ampton: Tune I2C AudioJustin TerAvest
The previous settings caused the I2C frequency for the audio bus to be too high, at 417kHz. The settings in this commit correct the frequency to 396kHz. BUG=b:119423345 Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-19soc/intel/icelake: Add GPIO group pad base for ACPISubrata Banik
commit msg copied from commit id: 64c9f1584c63403207ee85b1d54ca594ae1fbedf The GPIO drivers in Windows and Linux for the Icelake CPU have a sparse GPIO map and do not allocate pins contiguously. Each GPIO group is allocated as 32 pads regardless of whether the hardware actually has that many in the group. It appears this originated with a bug in Windows/UEFI and was carried over to Linux in order to work with existing firmware: https://lore.kernel.org/patchwork/patch/855244/ In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. Change-Id: I94fafd8af13cf229f5c467de5179aed021465739 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18Revert "google/sarien: Increase BIOS region to 28MB"Lijian Zhao
This reverts commit ad41f5512306d118047d2f7243678ddb32b4b06b. Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A> BUG=b:121169122 Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30286 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during bootTimothy Pearson
When the BMC firmware module is installed on the KGPE-D16, the RAM SPD multiplexer lines are disconnected by hardware from the SP5100 GPIOs and attached to BMC GPIO lines instead. Set the BMC GPIOs to match the state of the SP5100 GPIOs during RAM setup. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/19820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18southbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18northbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Icae59721db530572d76035975a4e90686bf4fa65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18cpu: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: I67bc60b9e0eb6289193d698787c18ea4593c991a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18soc: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: I64e061017ee0b1202ce5482b26c7550e4cd0f0a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18{drivers,superio}: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18nb/intel/haswell: Add server processor host bridge device IDIru Cai
The device ID is documented in "Intel Xeon Processor E3-1200 v3 Product Family Datasheet volume 2" section 2.2. Tested with ASRock H81M-HDS with Xeon E3-1271 v3. SeaBIOS payload can find the boot devices, and GRUB payload can boot Debian GNU/Linux on the SATA disk. Change-Id: I999391c9bbc6b39526ad7aec8a6d8fe1a9b5f921 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/30266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18mb/google/sarien/variants/arcada: Enable touchpad and touchscreenCasper Chang
Enable Elan touchpad and WACOM touchscreen BUG=b:119924134, b:120103010 BRANCH=master TEST=Verify touchpad and touchscreen on arcada work with this change. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa Reviewed-on: https://review.coreboot.org/c/30146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18soc/braswell: ensure ACPI opregion restored on S3 with GOP initMatt DeVillier
The Intel GMA ACPI opregion address needs to be set on S3 resume, otherwise the Windows display driver fails to re-initialize correctly. Fix by ensuring the address is set correctly regardless of display init type used (GOP or VBIOS). Test: build/boot on google/edgar, ensure internal display functional following S3 resume under Windows 10. Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18soc/baytrail: add vmx support via CPU_INTEL_COMMONMatt DeVillier
Mirrors addition to Braswell SoC in commit d3d0f07. Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows virtualization as enabled. Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18mb/google/kahlee/liara: Document why IOMMU is disabledJonathan Neuschäfer
Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU in all kahlee variants, but omitted the explaining comment only in liara's devicetree.cb. Copy this comment to liara. Change-Id: I564013a16217445003467e2a0579abd50597b205 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer
They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-18src/mb/google/*/Kconfig: Consistently use $(...) for variablesJonathan Neuschäfer
Using ${...} in some places is slightly confusing. Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree") Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18soc/amd/stoneyridge: Improve grammar through punctuationJonathan Neuschäfer
Change-Id: Iebae12f0b0397b5d4ad1fb09b5d9b847bc63c5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 08:27:03 +0000