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Change-Id: I4cf5cd1d3bed7188590e4f143d8f14dc9e58b183
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I2296ab3c53a82ee990649e35e1370e1dd304e392
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibbc010c9550c0a50b1e913e198f9b575107572fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4d0df30255d006c0399dde1b3ba8ee513d98dc0a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iba838309f8055d364c5f846ce29e628067d7b5f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This macro is no longer used since commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite").
Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
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Only input from the BJ port is wired to VSYS on Kalista. VBUS from
USB-C is for output only. In other words, Kalista is a source only
device from a USB/PD perspective.
This patch disables EC-EFS, which would be needed for the EC to jump
to RW to get PD power before the AP boots. Kalista will be always
supplied enough power to boot the AP through the BJ port.
CQ-DEPEND=CL:1330171
BUG=b:118386511
BRANCH=none
TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work.
Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29564
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot
Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.
Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/29570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0
for only 2nd SKU.
BUG=none
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/29631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The GPP_E1 gpio was incorrectly being defined as a no-connect.
Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic.
BUG=b:119508897
TEST=Build and flash nocturne, boot nocturne and
1) Verify nocturne can successfully suspend/resume from S3 and S0ix.
2) Verify wake from wlan wakes device from S3 and S0ix.
To do so,
a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT
b) connect DUT to mobile hotspot
c) sleep device via "powerd_dbus_suspend"
d) turn off hotspot, verify DUT wakes from S0ix
e) enable hotspot again
f) connect DUT to hotspot
g) sleep DUT via "sudo echo mem > /sys/power/state"
h) turn off hotspot, verify DUT wakes from S3
Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Ifae9d67bbba57b30ee9a2f31c448efcb27981c57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The common SPI controller driver in src/southbridge/intel/common does
match the SPI controller included in the PCH of Broadwell-DE SoC. Switch
to the usage of this driver and delete the dedicated one for the FSP
based Broadwell-DE implementation.
TEST: Boot mc_bdx1 with SPI driver active in romstage
Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29625
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Adjust the default fmap description file.
Tested on real hardware.
Change-Id: I46165eb27314a500187bcd24e3e201cf6a3175e7
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29596
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested - builds fine with this patch.
Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
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There are several files under soc/amd that use units defined by file
porting.h. These units use upper case, and are not recognized by checkpatch,
thus causing problems when defining a pointer (request to use space before
and after the star symbol). These are the definitions from porting.h showing
the units that this patch will change and their coreboot definitions (not all
are actually used):
typedef uintptr_t UINTN;
typedef int64_t INT64;
typedef uint64_t UINT64;
typedef int32_t INT32;
typedef uint32_t UINT32;
typedef int16_t INT16;
typedef uint16_t UINT16;
typedef int8_t INT8;
typedef uint8_t UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
typedef unsigned char BOOLEAN;
typedef void VOID;
BUG=b:118775313
TEST=Build and boot grunt.
Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Function write_pci_cfg_irqs() has "no function" variables. One variable is
set and never used, the other is only used to control a print. Remove them.
BUG=b:117950052
TEST=Build grunt.
Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Value stored to 'cmd' is never read
Change-Id: I794b6e12f5af272705cd996f7ca5099e9b9dbfc7
Found-by: scan-build from clang 6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/29568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I478a59534ec997947855eb0ff228a0dd9e15a5a5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/29567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Currently, there is nothing for this mainboard to do in ramstage.
Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard is equipped with LPDDR4 modules. The corresponding memory
swizzle data must be set for this purpose.
Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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BUG=b:118798180
TEST=emerge-octopus
Change-Id: I241a76e3b55ad721c6c0176462c310bcca6b3c5d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29503
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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OEM name can be stored in CBI. This change can support for fetching
the OEM name from CBI.
BUG=b:118798180
TEST=Verified to get data from CBI
Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Currently mode-aware DPTF depends on Tablet Mode Switch to load the
right table. This does not scale well with device types and configuration.
This change helps to decouple the mode-aware DPTF from Tablet Mode Switch.
This change allows ACPI to load the appropriate DPTF table based on the
profile number as detected by EC.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29249
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support Multi-DPTF profile, Device DPTF Profile Number is
introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset
0x09. This bit field stays along with Tablet Mode Device flag.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where
it is not required.
BUG=b:118149364
BRANCH=None
TEST=Build
Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support to log events during the preram stages.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ia69515961da3bc72740f9b048a53d91af79c5b0d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29629
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/
Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Current implementation works by luck as DCACHE area is actually RAM and
stack can grow and use that RAM outside of the area.
* Set DCACHE_BSP_STACK_SIZE to 0x4000.
* Add an assert to make sure it is set to a sane value on all platforms.
Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29611
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD".
BUG=b:119400832
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
mosys memory spd print all
0 | DDR4 | SO-DIMM
0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD
0 | 4096 | 1 | 64
0 | DDR4-1333, DDR4-1600, DDR4-2400
Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/29557
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After adjustment on aleena EVT
Audio: 390.0 KHz
H1: 390.0 KHz
TP: 399.8 KHz
TS: 399.8 kHz
BUG=b:116306959
BRANCH=master
TEST=emerge-grunt coreboot, scope measuring.
Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable the option to have the system level _PTS/_WAK methods call
the EC provided methods when they are invoked by the OS.
Verified on sarien board by inspecting dsdt.dsl:
Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep
{
DBG0 = 0x96
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
}
Method (_WAK, 1, NotSerialized) // _WAK: Wake
{
DBG0 = 0x97
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
Return (Package (0x02)
{
Zero,
Zero
})
}
Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a helper function specific to ramstage to add the boot count
information into event log at ramstage.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Group event log state information together to manage them better during
different stages of coreboot.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This implementation updates the GPIO pins, communities and
group mapping.
Change details:
1. Update 5 GPIO community includes 11 GPIO groups
GPIO COM 0
GPP_G, GPP_B, GPP_A
GPIO COM 1
GPP_H, GPP_D, GPP_F
GPIO COM 2
GPD
GPIO COM 4
GPP_C, GPP_E
GPIO COM 5
GPP_R, GPP_S
2. Update GPIO IRQ routing.
3. Add GPIO configuration for iclrvp board.
Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: If77c23fc5d440fe9181e4aae72ffff8ddaa716b6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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