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2019-01-07nb/intel/gm45: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27016 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07mb/google/hatch: Enable touch panel supportMaulik V Vaghela
Following changes are done to enable touch screen support on hatch 1. Enable I2C1 device at 400Khz at 3.3V 2. Configure GPIO for touch screen 3. Add ACPI entry for ELAN touch panel 4. update GPIO table with not connected GPIO pins for panel BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-07intel/lynxpoint: Fix spellingKyösti Mälkki
Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-07src/mb/asus/p5qpl-am/romstage.c: Fix commentAngel Pons
Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30705 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07usbdebug: Sanity check PCI EHCI locationKyösti Mälkki
If requested EHCI function is not on bus 0, we would need to open MMIO windows and configuration register space for the connected upstream PCI bridge for it to work. We don't plan to do so. Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-07usbdebug: Probe for gadget only onceKyösti Mälkki
The first stage attempting to initialise usbdebug gadget will leave it marked as non-present if none is detected. This allows further stages to bypass usbdebug init sequence. Change-Id: I1491d7fab3c89f210fb03b32481f697bc7a1d1e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-07usbdebug: Initialize the HW once in CAR stagesArthur Heymans
The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-07sb/intel/fsp_rangeley: Fix typo in GPIO LevelElyes HAOUAS
Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian
2019-01-07sb/intel/bd82x6x: Fix typo in GPIO LevelArthur Heymans
Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-07mb/google/poppy/variant/rammus: enable USB acpimarxwang
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:119899987 TEST=build and flash to rammus, log into rammus and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Signed-off-by: marxwang <marx.wang@intel.com> Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b Reviewed-on: https://review.coreboot.org/c/30607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Correct I2C bus clock for touchpadLijian Zhao
Elan touchpad require connected i2c clock to be running at 400Khz, with the modification can get 404Khz speed from Arcada EVT platform. BUG=b:119628524 TEST=Build and boot up on Arcada platform, measure the i2c clock is around 400Khz. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 Reviewed-on: https://review.coreboot.org/c/30653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Modify ELAN Touchpad i2c bus clkJohn Su
Modify ELAN touchpad bus i2c clk from 466Khz to 400Khz. BUG=b:119628524 BRANCH=master TEST=measure ELAN Touchpad CLK Change-Id: Ia8433c6ef320cea9a0145db4ba440d67ccd0f41e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30588 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07src: Use "foo **bar" instead of "foo ** bar"Elyes HAOUAS
Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-01-07src: Move constant to the right side of comparisonElyes HAOUAS
Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-07soc/intel: Standardize names of common MSRsElyes HAOUAS
Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-06soc/intel: Drop pmc_get_mainboard_power_failure_state_choice()Nico Huber
It's not needed anymore. Change-Id: I273acb2bf1675dc947927e3e6d2ebb78aa94518a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-06Kconfig: Unify power-after-failure optionsNico Huber
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06mb/google/slippy: Add a VBT for all variantsArthur Heymans
The vbt was extracted from the option rom found on stock images. The vbt.bin is the same across all variants. The VBT has a modified BDB block 43, the 'Backlight info block' such that the inverter type for the panel in use is set to 2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE). This only seems to matter on Windows, as without it changing the backlight duty cycle does not work. Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30487 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06superio/*: Link early initialization into bootblockArthur Heymans
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. It is likely unnecessary to do this in verstage. This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM. Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06mb/google/fizz: enable eist (enhanced speedstep)Matt DeVillier
Without eist enabled, fizz's CPU clocks are locked at the base frequency, and don't scale up or down. This prevents fizz from idling properly and turbo boost from functioning, so enable it (as is done for all other KBL boards) Test: build/boot google/fizz, ensure CPU clocks scale as expected Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.cAngel Pons
This is done for consistency purposes. Also fix a small formatting issue in a function. Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06usbdebug: Refactor init callsKyösti Mälkki
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06device: Use pcidev_path_behind()Kyösti Mälkki
Change-Id: Iac16f9412d0e6aac908d873c61a4de3935e5318a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26518 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-05cpu/intel/common: improve debug outputMatt DeVillier
currently, if the IA32_FEATURE_CONTROL lock bit is already set, VMX status isn't reported. Adjust debug output to provide more useful infomation on both VMX and lock bit statuses. Test: build/boot google/chell, observe useful output in cbmem log regardless of lock bit status. Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04mb/*/chromeos.c: Fix PRE_RAM and unify styleKyösti Mälkki
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30399 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04mb/google/jecht: Rename save_chromeos_gpios functionKyösti Mälkki
We have init_bootmode_straps() defined for the same purpose. Change-Id: Ia2692d8f8986247ea4ce889d6252d3c4c8b27bc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30398 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04AGESA: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26482 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04binaryPI: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04soc/intel/fsp_broadwell_de: Use BLOBs for microcode updatesPatrick Rudolph
Add possibility to update microcode from BLOBs repo. No need to copy headers around which have an unclear license. Tested on wedge100s: * Microcodes are included into FIT. * Still boots to Linux. * 3rdparty/blobs at dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1 Change-Id: I8ecfb7302a7fc847a51934942f6d323a4f96abba Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-04amdfam10 boards: Use defaults for get_pci1234()Kyösti Mälkki
Note that while these boards had entry 0x0ff0 in comparison to 0x0ffc of the get_default_pci1234() initialisation, the implementation of get_pci1234() unconditionally overrides the first entry. Change-Id: I8bec612f84fe3c3a0c21fc1e10629368857e9c5e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Use defaults for get_pci1234()Kyösti Mälkki
All these boards use the same default initialiser. As this is initialized late after device enumeration, it can't really be used to alter platform configuration. Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop array bus_sb700Kyösti Mälkki
Only bus_sb700[0] is evaluated. Change-Id: Ie2cbbdebed3ae03da916d02919cd6a5d36f53562 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop array bus_sb800Kyösti Mälkki
Only bus_sb800[0] is evaluated. Change-Id: I8ae0e6facbbe302b71692cf98a0292ee7d3bdca1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop array bus_sp5100Kyösti Mälkki
Only bus_sp5100[0] is evaluated. Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Add temporary pirq_router_bus variableKyösti Mälkki
It's expected that further analysis shows this to always evaluate to 0. Change-Id: I68599b961ca3b5e3652539c5d825a00444958d1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Use PCI_DEVFN()Kyösti Mälkki
Change-Id: I301ed4024f1dd6fb2009d59b2992830d4f17ee2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop array bus_sr5650Kyösti Mälkki
Values in the array are not used anywhere. Change-Id: Iee92f903db97533709d54d1f214f2f23a1fab06b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop array bus_rs780Kyösti Mälkki
Values in the array are not used anywhere. Change-Id: I608b8c2e21bc515c56a27982815c1da43f3bb976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop const variable sbdn_sp5100Kyösti Mälkki
Change-Id: I8756a81324ba3d4374bb6b06f7f0ddade6ba530f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop variable sbdn_sr5650Kyösti Mälkki
It mirrors value of sysconf.sbdn. Change-Id: I3ea42280a1bdceffebb6b5c85aee18347734ee4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop extern on bus_sr5650 and sbdn_sr5650Kyösti Mälkki
Change-Id: I3b95ec5746077b49cd6dca64d0f884a3d1c362fb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop variable sbdn_rs780Kyösti Mälkki
It mirrors value of sysconf.sbdn. Change-Id: I3cb611f1ea33da19e63523bc0fe99f2792eebc57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop const variables sbdn_sb800 and sbdn_sb700Kyösti Mälkki
They evaluate to const zero and obscure PCI_DEVFN() use. Change-Id: I8bd8dced62094d5ee8e957241ac29ead054f5c05 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop extern on bus_rs780 and sbdn_rs780Kyösti Mälkki
Change-Id: I7dc943f3376e9b706d3d486231525df85f806858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Call get_bus_conf() just onceKyösti Mälkki
It has to be called once before PIRQ and MP table generation. Change-Id: I238c6b4810404d320b36d4f6b4a161c1ff11c8d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Add Makefiles and fix resourcemap.cKyösti Mälkki
Also remove global ramstage-y += get_bus_conf.c, this is specific to amdfam10. Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04amdfam10 boards: Drop global bus_isa variableKyösti Mälkki
Value of the global is never evaluated. Change-Id: I74106b0f5f033053288882a5bcd3c1dba3235ac0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 20:09:47 +0000