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2019-07-30soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds readsJacob Garber
There will be a possible out of bounds array access if power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so prevent that in the index check. This issue was fixed for other cpus in commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one in condition). Based on the discussion for that commit, also remove the magic constant 28 in favour of the index of the last array element. Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30vc/cavium/{bdk,include}: Clean up bdk_phys_to_ptr() callsJacob Garber
The bdk_phys_to_ptr() function converts a uint64_t address to a void * pointer. Judging by the comments, the old implementation had a check that would refuse to convert a null pointer, which required several workarounds when trying to convert the address 0 to a pointer. This isn't the case for coreboot though, which implements this function as a simple (void *) cast, so we can remove the old workarounds. Change-Id: I6537d1699e6726c1fb155d69a51e14da856232de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393962 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30vc/cavium/bdk/libdram: Add array bounds checkJacob Garber
Ensure that best_en_idx is within bounds before accessing the _en array. Change-Id: Ifa6259e28875a8cf8199896bda7982370ccaa277 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30vc/cavium/bdk/libdram: Remove unused assignmentJacob Garber
The total number of errors is only needed after a final tuning run at the end of this function, so we can remove this unneeded store for earlier runs. Change-Id: I62adb38ccba98d90bcf8ccd13998762b9b694111 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393967 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30mb/emulation/qemu-riscv: Protect CBFS from payload loaderPatrick Rudolph
The virt machine is special as it doesn't emulate flash and it puts the coreboot.rom at start of DRAM. The payload loader doesn't know about CBFS in DRAM and overwrites the CBFS while decompressing payloads, resulting in undefined behaviour. Mark the region as SRAM to make sure the payload won't overwrite the CBFS while decompressing. As payload is always decompressed to DRAM, it wouldn't touch SRAM memory regions. Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29mb/emulation/qemu-riscv: Fix regressionPatrick Rudolph
Fix regression introduced in bd4bcab "lib: Rewrite qemu-armv7 ramdetect". The detected DRAM size is in MiB, thus needs to adjusted accordingly before passed to ram_resource. Wasn't seen earlier as everything works, except payload loading. Change-Id: I4931372f530e7b4e453a01e5595d15d95a544803 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29Revert "src/security/vboot: Add option to skip display init with vboot 2.0"Christian Walter
This reverts commit 598af2e2c2785c00eb4290cdcefe1082b2a6f858. Reason for revert: This commit breaks every board with VBOOT enabled if the platform is apollolake, broadwell, skylake, baswell, baytrails or icelake. The reason is, that the SoC selects VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if it is a CHROMEOS platform. Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29src/superio/nuvoton: Add support for NCT5539DPavel Sayekat
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29Revert "soc/intel/common: Set controller state to active in uart init"Christian Walter
This reverts commit 46445155ea21b0aa9106e12a00b9b1d89887a461. Reason for revert: Breaks coreboot. Either no UART working or the complete boot process stops. Platform: Intel Apollolake, tested on Up Squared Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-29soc/qualcomm/qcs405: Handle invalid QUP and BLSPJacob Garber
Print an error message and return if an invalid QUP or BLSP is encountered. This prevents a possible null pointer dereference of spi_clk. Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1401086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29soc/intel/baytrail: Prevent unintended sign extensionsJacob Garber
Consider the following assignment: u64 = s32 For positive values this is fine, but if the s32 is negative, it will be sign-extended in the conversion to a very large unsigned integer. This manifests itself in two ways in the following code: First, gpu_pipe{a,b}_port_select are defined as int, and can have the values 1 or 2. In the case when they have the value 2, the shift 2 << 30 will be a negative number, making it susceptible to the sign-extension problem above. Change these variables to something more reasonable like a uint8_t, which is unsigned. Second, in any bit shift, any variable with width less than an int will be implicitly promoted to an int before performing the bit shift. For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become negative, again introducing the above problem. To prevent this, cast all smaller variables to a u32 before the shift, which will prevent the implicit promotions and sign extensions. Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29src/mainboard/{cavium,sifive}: Use $(obj) instead of buildRaul E Rangel
The build directory might not exist in the src dir. BUG=b:112267918 TEST=make what-jenkins-does Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29soc/nvidia/tegra124: Assert divisor is non-zeroJacob Garber
The logic for the calculation of plld.m is rather complicated, so do a sanity check that it is non-zero before doing the division. Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1260981 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29vc/cavium/bdk/libdram: Print unknown voltagesJacob Garber
volt_str is used to print information about the RAM configuration in report_common_dimm(), so let's print out "unknown voltage" if the voltage isn't recognized rather than a garbage value. Change-Id: I8e85917fd682e166172fbf10597bde4a8a11dfc7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393958, 1393982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29haswell: reinitialize EHCI debug hardware after raminitIru Cai
Tested on Lenovo ThinkPad T440p. Change-Id: I54b0c9dbb64819f0f502783b632470d27ed0b2b1 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34358 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29mb/google/octopus: Add keyboard backlight supportWisley Chen
Dorp device support keyboard backlight, so enable it. BUG=b:138413969 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: If0c7b22b4be2a5d5216404a6944ac887883e9a47 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-07-29soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra
Change-Id: Id974a4bb84b7d5caddece04f93bf4e830d15b576 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28sb/intel/common/spi: Fix opmenu setupNico Huber
Remove a spurious reference: the `optype` field is already the pointer we want. Change-Id: I65eb3a519db9037c84750c5d40e3f19a1e360361 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-28riscv: Remove unused headersPatrick Rudolph
Change-Id: I4cd03e043e1bc2795b98d6ec2f88efa5b50d872b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-28lib: Rewrite qemu-armv7 ramdetectPatrick Rudolph
* Move armv7 RAM dection to a common place * Enable it for all emulated platforms * Use 32bit probe values and restore memory even on failure * Use the new logic on the following boards: ** qemu-armv7 ** qemu-riscv Tested on qemu-system-riscv: Fixes kernel panic due to wrong memory limits reported. Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-28mainboard/facebook/fbg1701: Add VBT binaryFrans Hendriks
Add VBT 8.0.1038 binary. Panel #10 is modified to support the 1200x1920 LCD panel. This panel is configured as default. LCD and HDMI are working fine. BUG=N/A TEST=booting Facebook FBG1701 Change-Id: If327e4e071df61b02fcec45213c2b700320ef269 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-26sb/intel/bd82x6x: Add support to disable xHCIPatrick Rudolph
Set FD bit if xHCI is disabled in devicetree. Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-26superio/fintek: Add f81803ARichard Spiegel
Add f81803A plus the capability to control the fan with any fintek SIO. This will be done through a common API, though currently only F81803A will have it implemented. BUG=none. TEST=Tested later with padmelon board. Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-26arch/ppc64: Make PPC64 stages select ARCH_PPC64Arthur Heymans
Also don't define the default as this result in spurious lines in the .config. This also cleans up an unused Kconfig file. In the generated config.h CPU_QEMU_POWER8 is gone as expected and ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same. Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-26soc/intel/baytrail/Makefile.inc: Sort entriesAngel Pons
Change-Id: Ic35a901c8272928a0389b38a74f4eac74977a080 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-26soc/mediatek/mt8183: Init SSPMErin Lo
Load SSPM firmware and boot up SSPM. BUG=b:80501386 BRANCH=none Test=We can see "SSPM is alive" in ATF stage if SSPM enabled and ipi success Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31835 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26soc/nvidia/tegra124: Correct bitwise operatorsJacob Garber
We are treating reg_val like a bit mask, so use bitwise or instead of boolean or, and use |= to enable certain bits instead of overwriting the whole variable. Change-Id: Ia8c0ea5a58e25b3b58ed82caba20f8e49a30fb68 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1287070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-26mb/google/hatch/helios: Update GPIO and device treeTim Wawrzynczak
Based on updated schematics, change polarity of USI_INT, and add the reset and enable GPIOs to the touchscreen ACPI node. The stop GPIO can't be used with the current implementation of _ON, as the way it's wired will cause power sequencing to fail. BUG=b:137133194, b:138240502 BRANCH=none TEST=Compiles, don't have next board rev to test with Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-26lib: add string.c to verstagePatrick Georgi
Change-Id: I5aa3bb2c72dcf127d418c989f6b63c9b1f412f08 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-26src/device/oprom: Fix bootsplash display code for optionromsJohanna Schander
So far the bootsplash is only correctly rendered if the framebuffer is set up as 1024x768@16. Different resolutions did not show anything, differnent depth resulted in the distorted images. This commit removes this limit by using the actual framebuffer resolutions and combines the code for x86 and yabel. For the moment the bootsplash is still limited to VGA-OptionROM framebuffer init. It was tested in 1280x1024@32 on the wip razer blade stealth using the intel vgabios. Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26oprom/yabel: Fix comment to fix the buildKyösti Mälkki
Old comment did not match the pattern required to not flag the fall-through as an error. Change-Id: I2afaca969c295a5dc4389dad0ce898c87bb841a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Johanna Schander <coreboot@mimoja.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-25ec/google/wilco: Hide wilco symbols when unusedElyes HAOUAS
This cleans up .config file from unused wilco symbols. Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/intel/fsp_broadwell_de: Fix use of config_of()Kyösti Mälkki
Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
Prevent implicit cast to pointers. The compiler doesn't warn about the conversion from integer to pointer without a cast, because SA_DEV_ROOT is literally '0' and there seems to be an exception for that conversion. Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/intel/broadwell: Fix case of SA_DEV_ROOTKyösti Mälkki
Commit 71756c2 soc/intel: Expand SA_DEV_ROOT for ramstage removed SA_DEV_ROOT expanding to device pointer. We missed the case here, use __SIMPLE_DEVICE__ instead for the file. Change-Id: I4331298837afa3b8c8321da610f99f8f5fa54737 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERBMatt DeVillier
Remove old hda_verb.c code copied from intel/kblrvp7, as it's been superseded by the common block HDA implementation. Fixes a null pointer error preventing the HDA codecs from being initialized, as found in Coverity CID 1403651. Test: build/boot Librem 13v2, verify functional audio Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/getac/p470: Remove unneeded whitespacesElyes HAOUAS
Change-Id: I8e36dc1553faa618aa852c06861029b4c0bdb27a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-25soc/{qualcomm,rockchip}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/mediatek: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Id6d881055826044d04843ba165641131b9111342 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/nvidia: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: I812d468c68b31917da5d406e2fb3b84bc6331b69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/qualcomm/ipq806x: Remove unnecessary allocationJacob Garber
The bus variable doesn't live outside the scope of this function, and is only used as a convenient way for passing the pointers to all the sub-functions, so it doesn't need to be allocated. Put it on the stack instead. Change-Id: I4370d77445952731d20f7d9a91803612f4d21aef Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel/cannonlake: Split the "internal PME" wake-up into more detailPaul Fagerburg
The "internal PME" wake-up source could be from integrated LAN, HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake. chromium:1680839 adds USB port details to the wake-up when the XHCI causes the wake-up. Expand the logging for wake-up details to identify and log the other wake-up sources with more details. Note that wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not in use on Hatch, so these will not be tested. BUG=b:128936450 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Program image-hatch.serial.bin into the DUT using flashrom. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). XHCI USB 2.0 * Plug a USB keyboard into a USB-A port * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Press a key on the USB keyboard * ``mosys eventlog list`` shows: 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 CNVi (connected to Wi-Fi): * Enable wake on disconnect via ``iw phy0 wowlan enable disconnect`` * Set up a hotspot on an Android phone * Connect the Chromebook to th hotspot * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Turn off the hotspot on the phone * ``mosys eventlog list`` shows: 8 | 2019-07-11 10:58:17 | S0ix Enter 9 | 2019-07-11 10:59:17 | S0ix Exit 10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0 11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109 XHCI USB 3.0 * TBD HD Audio * TBD Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/google/poppy/variant/nami: add sku ids of bardRen Kuo
add two sku ids of bard: 0x1009CE0 0x1009CE2 BUG=b:137892804 TEST=emerge-nami coreboot Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/nvidia/tegra210: Prevent unintended sign extensionJacob Garber
The perennial problem with u16 << 16 strikes again - the u16 is implicitly promoted to an int before the shift, which will then become negative if the highest bit of the u16 was set. Normally this isn't much of a problem, but in this case tegra_dsi_writel() expects a 64 bit integer for that argument, and so it will be sign-extended to a very large unsigned integer if it is negative. Cast bytes to a u32 beforehand to prevent the implicit promotion and thus this problem. Change-Id: Iaf0fb1040ccafafde0093e9bb192c802b86cb2ac Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34529 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/nvidia/tegra210: Add null pointer checkJacob Garber
Check that tx is not null before accessing it, similar to the previous if statements. Change-Id: I820cb670026bb12a54c63227aa04e778fd49c66a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/rockchip/rk3399: Use 64 bits in multiplicationJacob Garber
This multiplication is of the form u64 = u32 * u32. Despite being stored in a 64 bit variable, the intermediate value is still calculated using 32 bit math, which could possibly overflow. Cast one of the variables to a u64 to ensure it uses 64 bit math instead to avoid this. Change-Id: Ib08624812e933fdca5a51150ab36d3be49383326 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1375443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25soc/intel/icelake: Add ENABLE_DISPLAY_OVER_EXT_PCIE_GFX kconfigSubrata Banik
This patch creates new kconfig option to bring display over external PCI based GFX card. This kconfig to select required kconfig which are not default selected by VGA_ROM_RUN to launch legacy oprom from pci based GFX card. Change-Id: I8ebde69e38defbe3321eb5e5bbd632c209ae2cd8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-07-24device: Default to VESA/linear framebuffer for ChromeOSNico Huber
Building for ChromeOS implies the use of Depthcharge which doesn't support legacy text mode. Change-Id: I7fd82bfed1e59de2de75419cfaea6f0c19cfdf5e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34483 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-24soc/intel/common: Set controller state to active in GSPI initMeera Ravindranath
Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-17 17:17:20 +0000