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2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
This is as per Intel's suggestion on how to display their name strings. Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1298 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
Dump and disassemble ACPI tables and look in _CST. In the last entry the state was getting set to 0: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000000, // State 0x0000005A, // Latency 0x000000C8 // Power } Now it is properly identifed as state 3: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000003, // State 0x0000005A, // Latency 0x000000C8 // Power } Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1297 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24Remove unused free() functionStefan Reinauer
Since coreboot is running very short, we don't free memory. Hence, drop (dummy) free() Change-Id: I6e2737f07c6b9f73ebfad7d124b97a57cb7454a3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1274 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Add standard header to prevent multiple inclusionVadim Bendebury
This include file needs to be prevented from being included multiple times. Change-Id: I42e0cbe38d332b919f22e331eaf7a0251929e1dc Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1293 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24Move GGL0001 ACPI code to generic ChromeOS codeStefan Reinauer
The only difference in this code on all our platforms is the array describing the GPIOs. Hence, only keep that array in the mainboard ChromeOS directory and move everything else to generic ChromeOS ACPI code. Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Fix MRC cache update delaysStefan Reinauer
When no valid MRC cache area is found, the mrc_cache data structure was used without prior initialization. This sometimes caused a long delay when booting because compute_ip_checksum would checksum up to 4GB of memory. Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1277 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
There are several reasons for this: 1. It's a core setting, not a platform setting, which is bizarre. But, we disable vmx via an SMI, and that only happens on core 0. Hence, the code did not correctly make the same settings on all cores- one had them disabled, the others were in an unknown state. When (e.g.) kvm started on a vmx-enabled core, then moved to a vmx-disabled core, the processor would reset *very* quickly. Changing this would be messy. 2. On the CPU on link, there is something about trying to set the lock bit that is getting a GPF. 3. It's the wrong place and time to set it. Once controlled, they can't be changed in the kernel. The kernel is what should control this feature, not the BIOS, as we have learned time and time again. If somebody is in as root and can start a VM, you have a lot more to worry about than someone starting a guest virtual machine. Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1276 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24malloc/memalign: Remove unneeded linker checkStefan Reinauer
This check got in the code when some Linux distros shipped broken linkers around 1999. Since then, the code around that check was changed, and it does not make sense anymore to have this check. Change-Id: I37c6b690d72f55c18ba4c34e8541a6a441e5e67a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1275 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SPI flash layer: remove unused function spi_flash_free()Stefan Reinauer
We don't ever free memory in coreboot, hence drop spi_flash_free() and spi_free_slave() Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1273 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
It's not really useful anymore I guess, and it makes the log files harder to read. Hence dropping it. Change-Id: If4c3e8b40ae491ca527ef62f8145206960f6579d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Make memalign print useful messages on failureRonald G. Minnich
Brevity is the soul of wit, except for error messages; then it's a sign of witlessness. I can say this because this error message may be my fault, although it is lost in the 20th century code base so who knows. Anyway, when memalign dies, it's not a bad idea to have a lot of information about what went wrong. So instead of the terse single bit of "something failed" this patch changes things to be a bit more useful. Change-Id: I8851502297e0ae9773912839ebfdf4f9574c8087 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1270 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24SandyBridge: Add another PCI device ID for northbridgeWalter Murphy
Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46 Signed-off-by: Walter Murphy <wmurphy@google.com> Reviewed-on: http://review.coreboot.org/1269 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24Fixes to enable RC6 on IvyBridgeDuncan Laurie
- The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1268 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
In order to be able to use udelay in code running on AP cores the timer has to be initialized on the according local APICs or the system will just hang when udelay is used. Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1267 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-23AMD and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in AMD northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1233 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-07-22i945: Disable IGD if plugin VGA is preferredPatrick Georgi
It's shut down, but UMA memory is not reclaimed. A later extension could optionally do the magic register dance that allows initialization of IGD as secondary graphics device. Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1252 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-22AMD CPUs: Updated CPU list in powernow_acpi.cJukka Rantala
Updated P state table to make frequency scaling work. Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf Also wrote a Python script for parsing AMD docs, but not sure where to put it: http://pastebin.com/1dSvkXwc Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e Signed-off-by: Jukka Rantala <jukka.rantala@gmail.com> Reviewed-on: http://review.coreboot.org/1244 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-22Simplify VGA card discoveryPatrick Georgi
We were handling vga, vga_first, vga_last, vga_onboard just to determine an onboard chip and the first plugin card. We were also traversing the devices manually instead of using the utility functions we have, for the chance that there are non-VGA cards we need to cope with (but why would they require VGA-style handling?) Change-Id: I8aa73aefa102725a64287f78a59de3d5dda1c7f2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1255 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-22Mainboard Parmer based on Trinityzbao
Parmer has. 1. Trinity, Socket FS1R2. 2. Hudson A75. Ubuntu has been validated on Parmer. S3 is supported. Change-Id: I1a6932d0ca9f7abe78dc24d3bc238a4b5a48281b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1158 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-22Trinity wrapper code improvement.zbao
Set the default location of hudson firmware to 3rdparty. Move UMA code from mainboard to northbridge. Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1241 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-20Fix udelay() implementation for i945 romstageNico Huber
Work around 32-bit overflow with 64-bit multiplication. Calculate correct CPU frequency. Change-Id: I86d78f2d70b9f9c62fd4e1e0d765e92e4de83f67 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20Allow shutting down internal graphics if plugin graphics are preferredPatrick Georgi
VGA is this part-legacy thing that can cause trouble... For this, introduce device_t->disable(dev) method, in which a driver can take care to deregister the device if necessary. Change-Id: I3fecec07f402e530458b79eda30b2c274101fefa Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20Allow YABEL to fake write accesses to config spacePatrick Georgi
A new Kconfig option tells YABEL to succeed on write accesses on other devices' config space without performing the actual write. This is enough for some basic bus modification done by some Option ROMs. Change-Id: Iab04f3a5c350b96654da4ba26858037f4c4b5c0a Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1249 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20Drop VGA_BRIDGE_SETUP config optionPatrick Georgi
It defaults to true, and isn't disabled anywhere in the tree. I also couldn't think of a case where it's actually useful. Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20Intel SCH northbridge: fix resource indexKyösti Mälkki
Change-Id: If131ac9df89080faccd8ed952d6fc019483b5b2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-19Add missing quote.zbao
Remove the menuconfig warning which comes up every time. src/mainboard/asus/Kconfig:85:warning: multi-line strings not supported Change-Id: I0ec0a0b625a33edd1d9b250a26aa3e0f42142eca Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1240 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-18AMD northbridges: drop dead codeKyösti Mälkki
Change-Id: I03949722ac3a127319a0ad3f812d77ba7b8f139f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1187 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Drop invalid device ops on Agesa northbridgeKyösti Mälkki
One could not pass a device of type APIC to PCI resource functions. The correct CPU model specific cpu->ops is set at later time in cpu_initialize(). Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
Northbridge code incorrectly adjusted the last cacheable memory resource to accomodate room for UMA framebuffer. If system had 4GB or more memory that last resource is not below 4GB and not the one where UMA is located. There are three consequences: The last entry in coreboot memory table is reduced by uma_memory_size. Due the incorrect code in northbridge code state.tomk, end of last resource below 4GB, had not been adjusted. Incrementing that by uma_memory_size diverts a region possibly claimed for MMIO to RAM, as TOP_MEM is written. Since the UMA framebuffer did not have IORESOURCE_CACHEABLE, it was ignored from the MTRR setup and not set uncacheable. The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs, should be copied from BSP to all APs instead of deriving the data separately for each Logical CPU. Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1217 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16AMD MTRR: fix rounding and renamesKyösti Mälkki
Use state.tomk to refer TOP_MEM, largest RAM address below 4GB. Use state.tom2k to refer TOP_MEM2, largest RAM address above 4GB. When setting either TOP_MEM or TOP_MEM2, any RAM resource found must fit below the set value. Thus, round register value upwards, not downwards. Change-Id: I436c1b3234c911680ce8b095052f8d71f40113e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
If northbridge called uma_resource() a resource of this type should be found when walking the resources list. For now, be rude and don't even try to combine it with neighboring regions. As the type is un-cacheable it is dominant over other MTRR setups claiming the same region. Change-Id: I57805e7e7da0709f8ed78d8df62c2abf22172a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Change uma_resource() to use new type IORESOURCE_UMA_FB.Kyösti Mälkki
MTRR setup code can detect this and mark it as UC/WT/WC as suitable for the specific hardware. Change-Id: Ib7a3d450fc7c19e3ca72767dfb350412dd35c971 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1214 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
These boards had identical UMA code: amd/dbm690t amd/pistachio technexion/tim5690 technexion/tim8690 The ones below had whitespace or debug level change compared to the one above: kontron/kt690 siemens/sitemp_g1p1 These boards use AMDFAM10 guidelines in code: asrock/939a785gmh amd/mahogany Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to AMDFAM10 northbridgeKyösti Mälkki
Following boards had identical code: advansus/a785e-i amd/bimini_fam10 amd/mahogany_fam10 asus/m5a88-v avalue/eax-785e gigabyte/ma78gm iei/kino-780am2-fam10 jetway/pa78vm5 Following boards had identical code: amd/tilapia_fam10 asus/m4a78-em asus/m4a785-m gigabyte/ma785gm gigabyte/ma785gmt In between the two, only whitespace difference. Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to Agesa Family14 northbridgeKyösti Mälkki
Following boards had identical code: amd/inagua amd/persimmon The following had only whitespace or debug level changes compared to ones above. amd/union_station amd/south_station asrock/e350m1 Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to Agesa Family12 northbridgeKyösti Mälkki
Change-Id: Ieaf284c207f0cd4b2f6b804c52f949c16435d823 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to Agesa Family15 northbridgeKyösti Mälkki
Change-Id: I5705623f5067823fae5986b3bcde58504a463508 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Add global uma_resource()Kyösti Mälkki
Like ram_resource(), but reserved and not cacheable. Switch all AMD northbridges to use this one. Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16i5000: Fix resource allocationSven Schnelle
The current code didn't reserve static resource the right way. Also reduce TOLM to 0xd0000000, because those boards have so many PCI devices that 0xe0000000 isn't sufficient. Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1220 Tested-by: build bot (Jenkins)
2012-07-15Poison the stack to uncover programming errorsRonald G. Minnich
Code can easily make the mistake of using uninitialized values or, in assembly, mistakenly dereferencing stack pointers when an address is desired. Set the stack to a non-zero value which is also (by testing) a pointer which will crash coreboot if used. This poisoning has uncovered at least one bug. Change-Id: I4affb9a14b96611e8bf83cb82636e47913025a5d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1221 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-14Add ASUS DSBF mainboardSven Schnelle
Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1223 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14Supermicro X7DB8: Use autogeneration of mptableSven Schnelle
And fix the wrong indenting of devicetree.cb while at it. Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1222 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14AGESA F15 wrapper for Hudson.zbao
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper. Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14Remove useless file from building.zbao
Change-Id: I09c695347c04d7db9add2cbb687d59c829175cfc Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1224 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13Add preliminary support for Bachmann electronic OT200Christian Gmeiner
Linux boots fine :) Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13MPTAPLE: generate from devicetree.cbSven Schnelle
This patch adds support for autogenerating the MPTABLE from devicetree.cb. This is done by a write_smp_table() declared weak in mpspec.c. If the mainboard doesn't provide it's own function, this generic implementation is called. Syntax in devicetree.cb: ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN> The ioapic_irq directive can be used in pci and pci_domain devices. If there's no directive, the autogen code traverses the tree back to the pci_domain and stops at the first device which such a directive, and use that information to generate the entry according to PCI IRQ routing rules. Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1138 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13IOAPIC: hook up driver in KconfigSven Schnelle
Missed to add the driver to Kconfig and Makefile.inc. Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1219 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12Lenovo X60: correct SDHCI write protect polarityJonathan A. Kollasch
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/1205 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 03:35:54 +0000