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2014-01-31baytrail: initialize graphics before MRCAaron Durbin
The graphics device needs to have its resource contraints initialized before running the reference code. Right now just use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB GTT memory. BUG=chrome-os-partner:22869 BRANCH=None TEST=Built and booted. Noted amount of stolen memory matches configuration as well as BAR size within the graphics device. Change-Id: I328bf858f288363187cf705d6340947393b5ff10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170427 Reviewed-on: http://review.coreboot.org/4850 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31baytrail: cache ROM space early in bootblockAaron Durbin
Take advantage of the cache early in bootblock. The intent is to speed up cbfs walking when trying to locate romstage. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Change-Id: If03210103c9782390230915db3b4a9759d172dce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170426 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31baytrail: update microcode to version 313Aaron Durbin
B2 and B3 steppings are now bumped to version 313. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built. Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170425 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4848 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31baytrail: add initial supportAaron Durbin
The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30cpu/intel: allow non-packaged scoped turbo settingAaron Durbin
In the past the turbo disable setting (bit 38) of the IA32_MISC_ENABLES msr has been package scoped. That means knocking the turbo disable bit down enabled turbo for the entire package. Sadly, that's no longer true on all Intel processors. Therefore, allow non-packaged scoped turbo setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED Kconfig option. It defaults to false which was the original assumption. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and ran both ways successfully. Change-Id: I71a31e76ff47878023081fc47da643187517b597 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182405 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5047 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30x86: Add SMM helper functions to MP infrastructureAaron Durbin
In order for the cpu code to start SMM relocation 2 new functions are added to be shared: - void smm_initiate_relocation_parallel() - void smm_initiate_relocation() The both initiate an SMI on the currently running cpu. The 2 variants allow for parallel relocation or serialized relocation. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi using these functions. Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173982 Reviewed-on: http://review.coreboot.org/4891 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30x86: add SMM save state for 0x0100 revisionAaron Durbin
The Bay Trail SMM save state revision is 0x0100. Add support for this save state area using the type named em64t100_smm_state_save_area_t. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted using this structure with forthcoming CLs. Change-Id: Iddd9498ab9fffcd865dae062526bda2ffcdccbce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173981 Reviewed-on: http://review.coreboot.org/4890 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30x86: parallel MP initializationAaron Durbin
Provide a common entry point for bringing up the APs in parallel. This work is based off of the Haswell one which can be moved over to this in the future. The APs are brought up and have the BSP's MTRRs duplicated in their own MTRRs. Additionally, Microcode is loaded before enabling caching. However, the current microcode loading support assumes Intel's mechanism. The infrastructure provides a notion of a flight plan for the BSP and APs. This allows for flexibility in the order of operations for a given architecture/chip without providing any specific policy. Therefore, the chipset caller can provide the order that is required. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted on rambi with baytrail specific patches. Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173703 Reviewed-on: http://review.coreboot.org/4888 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
Haswell was the original chipset to store the cache in another area besides CBMEM. However, it was specific to the implementation. Instead, provide a generic way to obtain the location of the ramstage cache. This option is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM Kconfig option. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with baytrail support. Also built for falco successfully. Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172602 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4876 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30x86: include optional reference code blob in cbfsAaron Durbin
In order to incorporate external blobs into CBFS besides MRC have a notion of a reference code blob. By selecting HAVE_REFCODE_BLOB and providing the file name the refcode blob will be added to cbfs as a stage file. BUG=chrome-os-partner:22866 BRANCH=None TEST=Using this option and other patches able to build, boot, and run blob code. Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174423 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4895 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30chromeec: allow override of i8042 interruptAaron Durbin
Some boards need to override which IRQ the i8042 keyboard controller has its interrupt on instead of the default IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard an ability to override the interrupt location. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi using this option. New IRQ is correctly picked up by kernel allowing keyboard support. Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf Reviewed-on: https://chromium-review.googlesource.com/177222 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4978 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30chrome ec: Fix ASL to use IO() instead of FixedIO()Duncan Laurie
FixedIO seems like a nice short version of IO but in reality it is limited to 10-bit ISA addresses and so should not really be used in most situations. Change all the references to use IO() directly instead. BUG=chromium:311294 BRANCH=none TEST=emerge-samus chromeos-coreboot-samus and check for iasl warnings using updated iasl compiler revision 20130117. Boot the imge and ensure that EC regions are still exported in /proc/ioports. Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174810 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4910 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30chromeos: provide option to identify reference code blobAaron Durbin
Certain platforms need to have reference code packaged and verified through vboot. Therefore, add this option. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built. Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180025 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5022 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30cbmem: Export ACPI GNVS cbmem pointer in coreboot tableDuncan Laurie
This will make it possible for payloads to find the ACPI NVS region which is needed to get base addresses for devices that are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5015 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30vboot: provide empty vboot_verify_firmware()Aaron Durbin
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being selected allow for calling vboot_verify_firmware() with an empty implementation. This allows for one not to clutter the source with ifdefs. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded call to vboot_verify_firmware(). Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172711 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4879 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30VBOOT: Set virtual recovery switch based on EC Software SyncDuncan Laurie
The Virtual Recovery switch flag needs to be set in coreboot since it is passed through directly to VBOOT layer by depthcharge. Rather than add a new config option we can assume that devices with EC Software Sync also have a virtual recovery switch and set the flag appropriately. BUG=chrome-os-partner:25250 BRANCH=all TEST=build and boot on rambi, successfully enter developer mode Change-Id: Id067eacbc48bc25a86887bce8395fa3a9b85e9f2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183672 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5061 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-29AGESA boards: Clean up definition of BIOS_SIZE in platform_cfgEdward O'Callaghan
Clean up vendor code from hard coded #define if-def chain with a pre-processor shift and subtract. Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4811 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28rmodule: consolidate rmodule stage loadingAaron Durbin
There are 3 places rmodule stages are loaded in the existing code: cbfs and 2 in vboot_wrapper. Much of the code is the same except for a few different cbmem entry ids. Instead provide a common implementation in the rmodule library itself. A structure named rmod_stage_load is introduced to manage the inputs and outputs from the new API. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted successfully. Change-Id: I146055005557e04164e95de4aae8a2bde8713131 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174425 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4897 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28spi: Add support for Winbod W25Q64DWAaron Durbin
The W25Q64DW spi part is programatically equivalent to the other W25Q64 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. BUG=chrome-os-partner:22292 BRANCH=None TEST=SPI controller can program the part. Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170011 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28cbmem: add reference code idsAaron Durbin
In order to identify the ram used in cbmem for reference code blobs add common ids to be consumed by downstream users. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted with ref code support. Noted reference code entries in cbmem. Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174424 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4896 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-28x86/mtrr: don't assume size of ROM cached during CAR modeAaron Durbin
Romstage and ramstage can use 2 different values for the amount of ROM to cache just under 4GiB in the address space. Don't assume a cpu's romstage caching policy for the ROM. Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4846 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-28intel: fix microcode compilation failure in bootblockAaron Durbin
When not building with CONFIG_SSE there are not enough registers for ROMCC to use for spilling. The previous changes to this file had too many local variables that needed to be tracked -- thus causing romcc compilation issues. Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4845 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28bachmann/ot200: Fix cmos.layout.Vladimir Serbinenko
In current cmos.layout baud_rate overlaps with hardcoded reboot byte. Fix the layout and provide the default for upgrade. Change-Id: I979b8743c4aab6f17b3acf61b92a74a333203379 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4804 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2014-01-28chromeos: include stddef to fix compilation errorAaron Durbin
As some of the standard definitions were shuffled around chromeos started failing to build. Correct this. Change-Id: I9927441ccb2d646e8b3395e6e9f8e8166de74ab0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4844 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28x86: include header to define types in useAaron Durbin
The tsc header is using u32 w/o including the file with defines it. Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4843 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27coreboot_table: don't add CMOS checksum twice.Vladimir Serbinenko
Checksum is already in cmos_layout.bin. No need to add it twice Change-Id: I6d12f35fd8ff12eee9a17365bbfab38845c09574 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4829 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27siemens/sitemp-g1p1: Add missing boot_option option.Vladimir Serbinenko
Unlike other additions this doesn't require versionning first since the bootblock reads it anyway from this hardcoded offset. Change-Id: I3e3f65602bb1b92b91097692ee13e6948a748061 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4832 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-27sitemp-g1p1: Migrate to new cmos.default approachVladimir Serbinenko
Current code just prints warning, defaults match the behaviour of current code when checksum is incorrect and look sane. Change-Id: Icda0d3cb3517fc15e6a0ee787b00276d2d435776 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4827 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27superio/fintek: Add initial support for Fintek F71869AD.Edward O'Callaghan
Change-Id: I41f1ee20517dd179a4dee914ab7f6332739e326e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4784 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26google/stout: Provide cmos.defaultAlexandru Gagniuc
Change-Id: Ief0d08e0cd3dc469d700acf8567435894651171e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4822 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-26google/butterfly: Provide cmos.defaultAlexandru Gagniuc
Change-Id: I0ec0d80f6c6682a0d3656a0c0743d166b1bc85c2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4820 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-26lenovo/t60: Add CMOS defaults.Denis 'GNUtoo' Carikli
The code for handling the invalid CMOS space in mainboard.c is now useless and so it was removed. Change-Id: I86ec6a7f73e32948adff9087d4af5372a49a46a5 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3520 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-26pc80/keyboard: Ignore interface test failure.Vladimir Serbinenko
On Asus A8N-E this test fails but if failure is ignored keyboard works. Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4816 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26asus/a8n-e: Implement basic ACPI.Vladimir Serbinenko
Change-Id: I3c8fa1fbec2175787666697f2239abb70020019e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4819 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26asus/a8n-e: Add IRQ for onboard audio.Vladimir Serbinenko
Now onboard audio works. Change-Id: I1a598390c980287744689011b40210cec0145c6a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4818 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26asus/a8n-e: Fix GPIO resources.Vladimir Serbinenko
Allocator can't currently handle both PnP and PCI resources together. Only 2 resources in PnP are not fixed. So fix them. Change-Id: Iad695d1d991d110b726ec429fff87c616af5ac8b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4815 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26asus/a8n-e: supply cmos.defaultVladimir Serbinenko
Change-Id: Ib54cda60c9d8c57885c2b62f978222e01c1c3347 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4814 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4805 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-24nb/sandybridge: Move MRC cache above mrc.binAlexandru Gagniuc
This small change greatly reduces CBFS fragmentation. There is now a small gap of only 728 bytes between mrc.bin and mrc.cache, with the 64 KiB alignment maintained for mrc.cache -- assuming systemagent-r6 is used. The gap was just under 64 KiB before. With this change, it is easier to accommodate fallback and normal boot stages without having to manually place the stages in the highly fragmented CBFS. Change-Id: Ia2340c1928ed6e232949e053d1943c2f5737f741 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4763 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-24asrock/e350m1/board_info.txt: Specify ROM socket and Flashrom support.Vladimir Serbinenko
Based on info by Kevin O'Connor. Change-Id: I21d447fec976e0ee967ba64b0f506c97c22917a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4765 Tested-by: build bot (Jenkins) Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-24asus/a8n-e/board_info.txt: Set ROM Protocol.Vladimir Serbinenko
Change-Id: I65f2faee672d4d7dea50b67cf6426f503034b380 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
Not used anymore since microcode was moved. Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4788 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23sandy/ivy SPI: Support hardware sequencing and use with multiple chipsVladimir Serbinenko
When 2 chips are present to get to the second one you have to use hardware sequencing. Also use it as the fallback if chip is unknown. Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger distributed under compatible license. Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M) Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4613 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23SPI: Add API for programmer-specific flashing.Vladimir Serbinenko
Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4712 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23keyboard.c: fix coding style with indentAndrew Wu
Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3986 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-23dmp/vortex86ex: Initialize I2C controller base address/IRQAndrew Wu
Change-Id: Iefd6852f2300f703ebed8b52aee627107a024f85 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/4570 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23lenovo/x230: Enable wacom USB portVladimir Serbinenko
Based on lsusb -t info from David Schissler. Change-Id: I061881f531b11dc6f5f7719269cf9f3c9b0b99e1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4786 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23Multiboot: remove multiboot tables generation.Vladimir Serbinenko
GRUB2-as-payload doesn't use them. Libpayload can live with just coreboot tables if loaded as payload. memtest86+ can use them but is buggy with them. Solaris needs a huge boot archive not supported by coreboot and too big to fit in flash (dozens of megabytes). All-in-all looks like no users are left for this. Change-Id: Id92f73be5a397db80f5b0132ee57c37ee6eeb563 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-23lenovo/x230: Add missing copyright line.Vladimir Serbinenko
Change-Id: I5ecd25e23cebf83d4ae9300307aaac527e05c377 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4778 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-05 14:33:14 +0000