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2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs) This also modifies the send_jedec_cmd function as DDR3 dimms can have ranks mirrored which needs to be accounted for. The ddr3_emrs1_config array is placed externally since it is also needed for write leveling. Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24device: Always build device_simple.c for less code duplicationNico Huber
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24src: Add space after 'while'Elyes HAOUAS
Change-Id: I44cdb6578f9560cf4b8b52a4958b95b65e0cd57a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-24mb/intel/glkrvp: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
GeminiLake platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these for GeminiLake RVP board as these are not being used. Change-Id: I810809bf58198a028e6cfcdbd68887f5f154a0ad Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26469 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
ApolloLake based reef platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef variants as those are not being used. Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If36a879fbe7a93a214d74dbfa6fb3ee2d09a044a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24chromeec: Add support for controlling USB port powerEmil Lundmark
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be used to control the power state of up to 8 individual USB ports. Some Chromeboxes have their GPIO pins for controlling USB port power wired to the EC, so they cannot be accessed directly by coreboot. Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-24mb/intel/glkrvp: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I791a69aeca9b44daabc9a3e5fb9ac92e6b22f3e5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-24mb/nvidia/l1_2pvv: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ife8ca30322d83c6d9276e79c057f12a901d6e8f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26312 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/poppy: Enable SAR config on NamiAmanda Huang
This change enables SAR config on Nami with CHROMEOS option. BUG=b:75077304 BRANCH=master Change-Id: I8217333db2db6c0fd5e1c144dedd3692b1e1e6a3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23stoneyridge: Store wake parameters in NVSRichard Spiegel
ACPI _SWS needs information on PM1 and ACPI events (though events can be read directly). Unfortunately PM1 is cleared in normal path and in resume path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS. BUG=b:75996437 TEST=Build and boot grunt recording serial. Run suspend stress test, after 3 resumes closed file and examined for the message indicating what was being saved to NVS. Two different path, normal boot (first boot) and resume path had different PM1. Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23soc/amd/common/block/pci: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I82089475eb43d58303d1091f35aee06f1f04b4a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23soc/amd/stoneyridge/: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23sb/amd/rs780: Get rid of device_tKyösti Mälkki
Change-Id: Ica3b6f2d0b270930df77d528e70bd15972da8757 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23sb/amd/sr5650: Get rid of device_tKyösti Mälkki
Change-Id: If03864d5e32dfc4a2e5e11a96a4df62699ca4392 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23mb/siemens/sitemp_g1p1: Get rid of device_tKyösti Mälkki
Change-Id: I2362c46c0b525fa67833e52f210265da1926142c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-05-23mb/emulation/qemu-i440fx: Get rid of device_tKyösti Mälkki
Change-Id: I11c35d22d9a9cba3cdb6af0ec1d2c01de8c20b6e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23nb/amd/pi: Get rid of device_tKyösti Mälkki
Change-Id: I9b1c597f5c6995f19e9697e8aa698fa672a220b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23nb/amd/agesa: Get rid of device_tKyösti Mälkki
Change-Id: I5bd1c1cd71bd9541c1a95d444cd8d5ff40687dde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23mb/google/poppy/variants/nocturne: enable MKBPNick Vaccaro
BUG=b:79617938 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", flash nocturne, boot to kernel, run evtest and verify that cros-ec-buttons is present and functional. Change-Id: Id710782e1f4e18eaac2a90c7c0f91af5223dbce3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: enable I2C #5 busNick Vaccaro
Enable I2C #5 for rear camera and SAR. BUG=b:79784124 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5 is detected. Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: deassert audio amp resetNick Vaccaro
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of reset. BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel, and verify sound works via "aplay /dev/random" Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: add touchscreen register infoNick Vaccaro
- add ACPI register information for touchscreen WCOM digitizer BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify touchscreen on Nocturne board works. Change-Id: I9790a930e8ed2748d568ce58c931ce34b3e22007 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23sb/intel/i82801dx: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I36f064b67f14556e38b41b7f64c3e27d8d935367 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-23sb/intel/i82870: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-22soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI InitSrinidhi N Kaushik
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table entry for this range which caused a page fault. Since this test is anyway not exhaustive, we will skip the memory test in FSP. There is an option to do PCIe power sequence from within FSP if provided with the GPIOs used for PERST to FSP. Since we do this from coreboot, will skip the PCIe power sequence done by FSP. FSP does not know what the clock requirements are for the device on SPI bus, hence it should not modify what coreboot has set up. Hence skipping SPI clock programming in FSP. CQ-DEPEND=CL:*627827 BUG=b:78599939, b:78599576, b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26284 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.3 for Gemimilake CQ-DEPEND=CL:*627827 Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26285 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22soc/nvidia/tegra(124|210): Add distclean targetsMartin Roth
Add distclean targets so these can be called by the junit.xml test target needed for jenkins testing. Change-Id: I5991b43503da1778a6d74a57fbc0daf862e570d7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-22src/device: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. The function prototype for "struct device *add_cpu_device" is already correct and doesn't need to be fixed. Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22sb/intel/i82801gx: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iccddf3140fd94c2e5a246fe2839573f5dd387147 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22sb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22sb/intel/fsp_bd82x6x: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I499414c067b06fa94b53832894e804118f7c3e80 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22device/device_util.c: Remove space after sizeofElyes HAOUAS
Change-Id: Ic8b77c78739badbea398053944484a55f715d03d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22sb/ti/pci{1x2x,i7420,xx12}: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I37c6db65be4477dabb6064c3cc7ea1c63e467d19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22sb/broadcom/bcm5785: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ia39347f9d07bb0055ea4686a8b319f323f68062e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22sb/broadcom/bcm5780: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ia46b909c78086d9417cabc1cd65e16d264a8df8e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate latest FSP builds with debug. CQ-DEPEND=CL:*627827 Change-Id: Ic0eb9254421e99c8d204d8dbb86e6c6c2ec8719c Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22stonyridge: Add TP_Perf_STRUCT structRaul E Rangel
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed everything that we don't need. I did have to change MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00. This struct is used to extract the timestamps from AGESA. BUG=b:64549506 TEST=built on grunt Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22amd/stoneyridge: Increase SMM reserved memoryMarshall Dawson
Add 64KB to the reserved memory used for stage_cache. This corrects an error observed when using a debug build of the AGESA blob. Messages on initial boot AGESA: Saving stage to cache Error: Can't add stage_cache 57a9e101 to imd and during resume AGESA: Loading stage from cache Error: Can't find stage_cache 57a9e101 in imd TEST=boot/suspend/resume Grunt with debug and release builds BUG=b:79154155 Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22mainboard/google/kahlee: Update RW_LEGACY size in fmapMartin Roth
Add the unused space to the RW_LEGACY area. BUG=b:79433466 TEST=None Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22google/kahlee: Swap UNIFIED_MRC_CACHE and RW_SECTION_A in fwmapDaniel Kurtz
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or RW_SHARED to be 0-sized, nor located at offset 0x00000000. Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test. BUG=b:79865447 TEST=test_that -b grunt ${IP} firmware_Mosys Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22rk3399: Enable bootblock compressionJulius Werner
This patch enables the new bootblock compression feature on RK3399, which requires moving MMU initialization into the decompressor stage and linking the decompressor (rather than the bootblock) into the entry point jumped to by the masked ROM. RK3399's masked ROM seems to be using a bitbang SPI driver to load us (very long pauses between clocking in each byte), with an effective data rate of about 1Mbit. Bootblock loading time (as measured on a SPI analyzer) is reduced by almost 100ms (about a third), while the decompression time is trivial (under 1ms). Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22Revert "program_loading: make types a mask, make unknown type a non-zero"Julius Werner
This reverts commit f3d99b6a657fe2bc3cff71956ab4f68fd1f287fe. Reason for revert: We're now doing this through CBFS types instead, so this shouldn't be needed anymore. Change-Id: I9e0d5446365f8ecc045615e4ba1a1313080c9479 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26448 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-21Revert "acpi: device: Walk up the tree to find identifier"Duncan Laurie
This reverts commit 8ccf59a94778fb54cc08368fb58a42b64d9489f6. This wasn't meant to be submitted yet and seems to be causing issues, just as Patrick warned me.. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I8c4b57ba92ef4e0535e4975485188114a1084f09 Reviewed-on: https://review.coreboot.org/26452 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-21nb/amd/amdk8: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If540a8b0afb93c1ba8e901c4771228a43c1e6a14 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-10 19:22:21 +0000