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2012-10-05YABEL: Common API to register interrupt handlersPatrick Georgi
Provide (mostly) the same API for registering interrupt handlers as with x86emu. Change-Id: I1364b08d9043039550786a1758508ae088813aa3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1558 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-04add tyan s8226: add a new mainboardSiyuan Wang
our code supports tyan s8226 now, which has two cpus on the board the cpu socket is C32. The details of tyan s8226 is: http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=679&SKU=600000190 the test result of this mainboard is: 1) boot Ubunbu 11.10, kernel 3.0.9. there is no err and warnings in dmesg. 2) boot windows7 x64 successfully. 3) use fwts to test the bios, there are 268 pass and 14 failed 4) pcie and usb slots are ok. 5) all network interfaces are ok. Change-Id: I7d8534f20b4f3c16322a5c5ba2e3fba4b4f3e608 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1495 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-04pirq_routing: Allow routing with more than 4 PIRQ linksAlexandru Gagniuc
pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1482 Tested-by: build bot (Jenkins)
2012-10-02Fix compilation without CONFIG_WRITE_HIGH_TABLES.Denis 'GNUtoo' Carikli
Without that fix we have: CC boot/hardwaremain.ramstage.o src/boot/hardwaremain.c: In function 'hardwaremain': src/boot/hardwaremain.c:136:6: error: 'cbmem_post_handling' undeclared (first use in this function) src/boot/hardwaremain.c:136:6: note: each undeclared identifier is reported only once for each function it appears in src/boot/hardwaremain.c:137:3: error: implicit declaration of function 'cbmem_post_handling' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make: *** [build/boot/hardwaremain.ramstage.o] Error 1 When compiling without CONFIG_WRITE_HIGH_TABLES Change-Id: Ie45f684a6db0ab55ef469bfcef57e539ae7e994c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1533 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-09-28AMD Hudson: Printf the high address as unsigned integerZheng Bao
Some 32 bit machines print integer higher than 0x80000000 as negative number. Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1547 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-25HAVE_HIGH_TABLES is gonePatrick Georgi
... but no-one told intel/sch. Change-Id: I68eaae6910bd6fc579c35b5bc038b9597cd1b3e7 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1537 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-24AMD hudson: Round the float pointing number to integerZheng Bao
Try sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \ $1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \ od -Ax -t x On Linux with gawk, we get 000000 005500aa 000004 On FreeBSD with nongnu-awk, we get 000000 000055aa 000002 In awk, all the numbers are floating point number. So division doesn't round the result from 0.75 (3/4) to 0. And, There is a fact that, for the FreeBSD awk, sh> awk 'BEGIN {printf("%c", 0.75)}'; produces nothing, instead of 0. Here we need to convert the floating point number to integer by int(X), which is an awk built-in function, instead of GNU extension. Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-09-19cimx sb700: change Platform.h to remove some warningsSiyuan Wang
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h, so we do some changes to remove such warnings. Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1499 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19agesa fam15 northbridge: change lapic_id to accommodate two CPUsSiyuan Wang
According to http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c;hb=HEAD#l273 line 273, adjust apic id to accommodate two CPUs. The Tyan S8226 has two CPU sockets, and the current code just finds one CPU's cores. we adjust apic_id in cpu_bus_scan so as to find all CPUs. Change-Id: Ib3263fc6f5508f744b81e8e388fde9ccd9b51851 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1498 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to ↵Siyuan Wang
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1497 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-17AMD Hudson: use awk to calulate instead of exprZheng Bao
Command expr in some systems only take 32bit as integer, which value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to calculate. And some system doesnt take hex value in Makefile, even in awk instruction. Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1527 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-17Set SMBIOS mainboard version based on i2c eepromChristian Gmeiner
In the field there are different hardware revisions and some of them have problems with UDMA as a resistor is missing. We can detect this situation in coreboot and e.g. the linux kernel can take this knowledge and disable UDMA. Change-Id: Ib75cad7acedbc1dc65378bb9bfc3f353cbe21427 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-17Add i2c eeprom to device treeChristian Gmeiner
This eeprom is used to store some device relevant informations like hardware revision. Change-Id: I32bda9d5412bc5a96da0edb5ef0b6d1ba4caa2d8 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1511 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-13Mahogany_Fam10: Fixes an apparent ACPI VGA resource collision.Dave Frodin
Without this change 64 bit versions of Windows will BSOD. Change-Id: If39627a179c24184b6c956b3a50f692f8a034d2f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1476 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-13Fix tracing compilation on SMM enabled targets.Rudolf Marek
Disallow tracing while in SMM. Change-Id: Icde17629bb06a615cc48f017fd0cd1f7b720e62d Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/1503 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-12Fix VT8237S USB IRQ routingRudolf Marek
The M2V-MX SE DSDT has been a copy from Asus A8V-E SE, which has VT8237R. But the stuble change in USB interrupt routing went undetected, although I had some USB troubles on the FOSDEM with low speed devices. Change-Id: Ie724df440e0963f6955b3de57e4687f3ddc7f6ef Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/1505 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-07superio winbond w83627dhg: add a function which is used on tyan s8226Siyuan Wang
this function is used on serial output of tyan s8226 Change-Id: I5f7fa535b922b224e381886f1bea64623fa549ef Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1494 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-09-06IEI/KINO: Fixes an apparent ACPI VGA resource collision.Dave Frodin
Without this change 64 bit versions of Windows will BSOD. Change-Id: Ica4b79d798a269399341868b1c793ce745aa93fc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1480 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-05VIA Nano: Add support for VIA Nano CPUsAlexandru Gagniuc
Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1257 Tested-by: build bot (Jenkins)
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1245 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-08-30AMD S3: The offset of the nv storage depends on config.hZheng Bao
Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1485 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-30ioapic driver: typedef the ioapic_config struct (TRIVIAL)Alexandru Gagniuc
I use the ioapic_config in my VX900 branch. Typing: struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; is clumsy at best, so just create a typedef to mahe this more elegant: ioapic_config_t config = (ioapic_config_t*)ioapic->chip_info; Change-Id: I407899845cfbd847ba6309dd0cf9ef836a607c8e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1481 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-28Fix AMD UMA for RS780Kyösti Mälkki
In commit 6b5eb1cc2d1702ff10cd02249d3d861c094f9118 setup of UMA memory region was moved to happen at a later state and this broke UMA with RS780 southbridge. Share the TOP_MEM and UMA settings before any of the PCI or CPU scanning takes place. Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1488 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-28AMD hudson: Complete the missing ruleZheng Bao
Forgot to change the code back after debugging. Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1491 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-27Drop unused ISA Pnp definitionsKyösti Mälkki
These declarations were never or no longer used. Change-Id: Icdbfc0838d5021ea02ab031b643b3fe6361b39b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1489 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27SB700/SP5100: This configures the HPET clock period.Dave Frodin
Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1475 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-27AMD Hudson: Move the combining firmware from Python to sh.Zheng Bao
Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1417 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27Intel model_106cx: change CAR to HT-capableKyösti Mälkki
There are hyper-threading Atom CPUs, those would not enable L2 cache with model_6ex CAR code. Switch to code that can handle different number of threads and cores. Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1384 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: James Laird <jhl@mafipulation.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27AMD northbridges: factor out CPU allocationKyösti Mälkki
Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1418 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27AMD northbridges: rewrite CPU allocationKyösti Mälkki
Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1186 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-25MPTABLE: check for fixed IRQ entries on all pinsSven Schnelle
Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1461 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-25Fix mptable build troublesKyösti Mälkki
A missing mptable.c file got passed jenkins, got merged and broke the build. Hopefully finally fix this. Deletes unused files: src/mainboard/asus/dsbf/mptable.c src/mainboard/supermicro/x7db8/mptable.c Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1486 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22LUMPY: Add information to generate MPTABLE from devicetree.cbSven Schnelle
Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1462 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22mptable: bring sanity back to mptable generation (TRIVIAL)Alexandru Gagniuc
Remove extra semicolon Capitalize beginning of printk sentence Fix detection of multiple ISA-carrying IOAPICs Fix whitespace issue Change-Id: I114119b1daf3b472955c0dd00bdc449401789525 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1474 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-21Change to allow coreboot to use "add-payload" instead of "add" for payload ↵Dave Frodin
images. The current code does some argument manipulation to detect when a stage is being added to cbfs. This same manipulation needs to be done when adding a payload. Change-Id: Ief4c4a81446c9437923cbbb1ce3fa90729317587 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1451 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-08-21Don't write automatic IRQ entries for disabled devicesSven Schnelle
Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-15coreboot: Dump memory around problem area when encountering exceptionAlexandru Gagniuc
When we encounter an x86 exception, we print the problem address, dump the registers and die. This may not be sufficient information for debug. Also dump the memory around the problem instruction. This has proven useful in identifying memory issues, and DRAM burst reordering problems. Change-Id: I6411344e89f946e16d11217d7dbd73812c45d54c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1454 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-13AMD Hudson: Enable HD audiozbao
Something about HD audio was scrubbed. Take it back. Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1427 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-08-09Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki
The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1387 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer
This was broken, fixing according to related patch for i945 Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1412 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Do not allow modifying memory table directlyKyösti Mälkki
Adding ranges directly into coreboot memory table raised issues as those methods bypassed the MTRR setup. Such regions are now added as resources, so declare the functions again as static. Change-Id: If78613da40eabc5c99c49dbe2d6047cb22a71b69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1415 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Fix SMBIOS generationStefan Reinauer
Dropping mainboard's chip.h broke execution of the mainboard's enable function and the addition of mainboard specific smbios tables. The former was fixed by Kyosti in http://review.coreboot.org/1374 This patch fixes the breakage in static.c and also backs out a small portion of Kyosti's patch (because it's not needed anymore) Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1421 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-07Siemens SiteMP: drop add_mainboard_resources()Kyösti Mälkki
Use of lb_add_memory_region() is reduntant with the MMCONF resource being set as reserved. Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1394 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer
The names were set at various times during development, but the way the code works, you might end up with the wrong name being displayed in the logs. Instead of doing magic, just display both names for each component Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1413 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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