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2014-08-21i945: Support text mode gfx initVladimir Serbinenko
Change-Id: I952fdb113e2696785695b416d9292b7107099994 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6723 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945/gma: don't map the page tableVladimir Serbinenko
Change-Id: I20fb5323cde1f83a3d3adc98251b2f31de25ed24 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Remove GTT avoidance offset.Vladimir Serbinenko
Not needed anymore with GTT at the end of range. Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6717 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-21arm: Get rid of the INTERMEDIATE variable used on exynos.Gabe Black
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for Exynos SOCs, but we can do that directly without having a special hook. Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-20intel/i945/gma: Place GTT below top of memoryPaul Menzel
Since commit 17fec8a0 [1] drm/i915: Use Graphics Base of Stolen Memory on all gen3+ present in the Linux kernel since version 3.12, 3D does not work anymore [2]. Comparing the graphics registers, in this case that means output of `intel_reg_dumper`, the vendor Video BIOS is setting the register PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init sets it to `0x3f800001`. Currently native graphis init sets the GTT right above the base address of stolen memory. The Video BIOS sets it below the top of memory. The Linux Intel driver expects it to be below top of memory, so do it this way, by setting the address to TOM minus the size of the GTT, which is hardcoded to 256 KiB. As `PGETBL_CTL` is zero by default, reading its value in the beginning is not necessary and is only confusing. Make it clear that the code calculates the value. There is still a PTE error reported during boot, but 3D works with Linux 3.12+ and no user visible problems are shown. [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038 [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/5927 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19tegra124: Implement the tegra i2c driver.Gabe Black
This uses the packet mode of the controller since that allows transfering more data at a time. Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172402 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6703 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.Gabe Black
The pins on tegra are controlled by three different units, the pinmux, the pin group controls, and the GPIO banks. Each of these units controls some aspect of the pins, and they layer together and interact in interesting ways. By default, the GPIOs are configured to pass through the special purpose IO that the pinmux is configured to and so can be ignored unless a GPIO is needed. The pinmux controls which special purpose signal passes through, along with pull ups, downs, and whether the output is tristated. The pingroup controls change the parameters of a group of pins which all have to do with a related function unit. The enum which holds constants related to the pinmux is relatively involved and may not be entirely complete or correct due to slightly inconsistent, incomplete, or missing documentation related to the pinmux. Considerable effort has been made to make it as accurate as possible. It includes a constant which is the index into the pinmux control registers for that pin, what each of the functions supported by that pin are, and which GPIO it corresponds to. The GPIO constant is named after the GPIO and is the pinmux register index for the pin for that GPIO. That way, when you need to turn on a GPIO, you can use that constant along with the pinmux manipulating functions to enable its tristate and pull up/down mode in addition to setting up the GPIO controls. Also, while in general I prefer not to use macros or the preprocessor when writing C code, in this case the set of constants in the enums was too large and cumbersome to manage without them. Since they're being used to construct a table in a straightforward way, hopefully their negative aspects will be minimized. In addition to the low level functions in each driver, the GPIO code also includes some high level functions to set up input or output GPIOs since that will probably be a very common thing to want to do. Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171806 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a) tegra124: Add base address for the pinmux and pingroup registers. There weren't any constants for the pinmux or pingroup registers in the address map header. Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62) Squashed two related commits. Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6702 Tested-by: build bot (Jenkins)
2014-08-19tegra124: Pick addresses to load the rom and ram stages.Gabe Black
If these aren't set, the rom and ram stages will attempt to load at address zero which doesn't work. Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/173540 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 6ac5cea39d423bfcf5bbd53c2cc6228ab89f08b2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6704 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19asrock/imb-a180/board_info.txt: add flash fieldsStefan Tauner
Change-Id: Ie686d20811f33c620156c149315807343dde7784 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/6700 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19macbook21: Support wake on LIDVladimir Serbinenko
Change-Id: Ifa1045abc761bef05977a8020cf6f18db042ad58 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6699 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x20[01]: Don't undock on disconnecting of power from dock stationVladimir Serbinenko
Change-Id: Id55bf259d5af187ba718de7e367395adcfc567b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6707 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Fix dock recognitionVladimir Serbinenko
Change-Id: I8b210786f660e2b2bae0d9ddd594386fd107cbe4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6706 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Unpower USB on undockingVladimir Serbinenko
Change-Id: I9b496e8ff92ee575d0b780eab0cb45ea05506d30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6708 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-19lenovo/x200: Dock supportVladimir Serbinenko
Change-Id: I4e25630ae82e8030a9d6bfccb60844c301b1d635 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18trustzone: Pull trustzone init out of cpu.c and do it in romstage.Gabe Black
Trustzone needs to be initialized/disabled both on boot and on wake, so it needs to be done before ramstage which doesn't run on wake. cpu.c isn't compiled into romstage and fixing that causes other problems, so the trustzone functions were split out. Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169817 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18tegra: Change how tegra124 and tegra include files from each other.Gabe Black
A problem with including the tegra124 directory directly in the include path is that it makes all headers in that directory first level headers available everywhere including places that have nothing to do with the SOC, even headers which were only intended for local use by tegra124 code. This change modifies things a bit to be more like the way the arch headers are chosen. In the tegra124 directory, there's an include directory which has an soc subdirectory in it. That include directory is added to the include path, making it possible to have headers private to the tegra124. When files specific to whatever tegra is being built for are needed, you can include <soc/foo.h> and get the version specific to that particular soc. Also, the soc.h header file was overhauled to use enums instead of defines, to consistently name things as far as their prefix (the less cryptic TEGRA instead of NV_PA) and suffixes like "BASE", and to get rid of values which were specific to U-Boot which we don't need. Since the only thing in the file were address constants, I also renamed the file addressmap.h. It would be included as: <soc/addressmap.h> which I think is easy to remember, does what you'd think it does from the name, and won't conflict with other header files just minding their own business in some other directory. Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172080 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5420: Don't map low addresses that lead nowhereJulius Werner
I just spent half a day (including the time to implement a stack dumper) to figure out that I am reading from a NULL pointer. A problem this simple should be more easy to catch. Let's mark the address range below SRAM as uncached so that the MMU can yell at you right away for being the bad programmer you are when you access a NULL pointer. Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170112 Reviewed-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6650 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18arm/exynos: Allow releasing UART retention for resume.Hung-Te Lin
The UART / serial console is put in retention state by kernel during suspend / resume path, which caused Coreboot not able to print any messages during resume. Sending values to the padret_uart_opt inside PMU may release UART, but that may also cause unexpected output when kernel is back. However, it's still very helpful when we are debugging suspend/resume inside Coreboot. To get UART message on resume, call wakeup_enable_uart() in boot block or romstage (before console_init). Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265 Reviewed-on: https://chromium-review.googlesource.com/170440 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6649 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5: Implement support for USB 3.0 DRD PHYs/controllersJulius Werner
This patch adds support for the DesignWare3 USB 3.0 DRD controller and PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the Google Snow and Pit boards to turn these controllers on where applicable. Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169452 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6642 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18console: conditionally include console in bootblockStefan Reinauer
Right now some console specific objects are included in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is disabled while others are not. Make all of them conditional and also fix a preprocessor misuse in bootblock_simple.c and a stray (useless) die() in the Exynos wakeup code that made inclusion of those files necessary. Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168772 Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6637 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-18macbook11: New mainboard (macbook21 clone)Vladimir Serbinenko
Tested by marcus. Change-Id: Ifce2018ef49619b36fb07e5345d70c358a0397e4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6698 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18mainboard/intel/mohonpeak: code cleanupMartin Roth
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18cpu/intel/fsp_model_406dx: code cleanupMartin Roth
Code cleanup requested in commit 09670265 - "cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)" - add guard statements to chip.h - remove excessive includes - whitespace cleanup - add an IS_ENABLED Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6599 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18apple/macbook21: Fix audio.Vladimir Serbinenko
Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5324 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-17Revert "macbook21: Add CST entries"Vladimir Serbinenko
Some of C-states still cause hang. Revert C-states patch. This reverts commit fe661612d8e94d41dc0129533bb02f7c4faaf11a. Change-Id: I7534dac5d27b853d7b93947c38bf3742797fdcc2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6694 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-08-17gm45: Declare BIOS memory as RAM.Vladimir Serbinenko
So it's in line with other boards and those addresses are cached for faster access. Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6689 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17macbook21: Add CST entriesVladimir Serbinenko
Change-Id: I9e8628d879a193e2f6ba561ee17f24ae94435e1a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6693 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17apple/macbook21: EC handling ACPI implementation.Vladimir Serbinenko
Now battery indicator and lid work. Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5323 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-17A new port apple/macbook21.Mono
Current problems: - Complete lack of EC support (no battery indicator, no temperature, ...) - No audio support Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/5321 Tested-by: build bot (Jenkins)
2014-08-17i945: Replace video gfx init.Vladimir Serbinenko
Old init was a replay not even meant to have been committed. This one really computes values and does its job. Tested on Macbook2,1 (1280x800) and X60 (1024x768). Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5320 Reviewed-by: Francis Rowe <info@gluglug.org.uk> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16AMD Family 14: Fix permissions on one northbridge fileBruce Griffith
fam14_callouts.h should not have the execute bit set. Change-Id: Iab44d04f2c9669e28d2d5028b0a11e565cc7bb07 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6675 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Decrease MTRR usageVladimir Serbinenko
Change-Id: I4c790b0eaf2af94286e6691281fcad3d14659a99 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6687 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I27b2ec70b9c77f3caf9d52788f46f5dc16045d1b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6686 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16lenovo/x200: Remove leftover roda rk9 devices.Vladimir Serbinenko
Change-Id: Ief3baa985cf83059255e64a8ab78cad9f8571199 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6688 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Recognize 48MiB gfx UMA.Vladimir Serbinenko
Change-Id: I33e6b357ea044d6ec00b119e84cbada7bf58317f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6685 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16intel/gm45: native gfx init.Vladimir Serbinenko
Tested on lenovo X200 in both text and gfx mode. Change-Id: I273971d0f34ca3529959d4228e9516775459b806 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16exynos5xx0: rename local "main" variablePatrick Georgi
Change-Id: I9a454c88c65e4e70d351f1ec781e75ba400ceb29 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6664 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16bootstate: don't use header in romstage codePatrick Georgi
Change-Id: I0c2943bb0889552dc384d8efb5226cd6982a4d81 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6663 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-15tegra124: fix Kconfig ARCH settingsIsaac Christensen
The initial commit for tegra124 (396b072) was not updated for the new ARCH settings. Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6658 Tested-by: build bot (Jenkins)
2014-08-15Move baytrail-specific config to baytrail.Vladimir Serbinenko
Stop polluting first screen of all boards. Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14armv7: mark EABI compatibility symbols as usedStefan Reinauer
These symbols are not used anywhere in our C code, so when using GCC's link time optimization feature they will be dropped even though they're needed by libgcc. Hence we need to mark them as used so GCC does not stumble and fall over its own guts. Change-Id: Ib2e9ea2610b57ab8244d5b699dd56025a4f08a01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168773 (cherry picked from commit 416ffc880bcf4122b5430fbd9d9547c83886af2f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14payloads/external/SeaBIOS: move build directoryIdwer Vollering
Move SeaBIOS' build directory out of build/ This allows the user to delete build/ in the top dir and keep the built binary in payloads/external/SeaBIOS/seabios/out/ Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-14Exynos: de-duplicate mct timer initializationStefan Reinauer
timer initialization is the first thing happening in the Exynos CPU's bootblock code. Hence we don't need to keep track of it in several places, and we don't need to do it over and over again (e.g. in each stage) Change-Id: I7bd9a0b7930fc9c37faabd62e3eecc3e5614a879 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168994 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5a95bc2bcab5a92c5e6c144005861bf731f59de3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14pit: snow: Fix snow, fix up pit write protect.Gabe Black
A recent change to support early firmware selection on ARM broke snow and was incompletely implemented on pit. This change fixes snow by applying the remaining part of the change that had been applied to pit, and also hooks up real values in the get_write_protect_state function. Change-Id: Ifef7ad1bf399f79353daec3dd46973f2b2022e37 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169120 Reviewed-by: David Hendrix <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 841773e048cd9cfbb64782059c24e29c467f17c8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-14lenovo/x200: Fix black screen on quick boot.Vladimir Serbinenko
Otherwise without USB when coreboot boots too quickly EC is confused and thinks that LID is closed and so powers off the backlight until user flaps the lid. Change-Id: I14dfaa62582de83fd4c9f9518e9436b3a3035366 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6651 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 08:00:45 +0000