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2020-07-22sb/intel/i82801jx: Drop `c3_latency`Angel Pons
The three mainboards using this southbridge do not define it. Note that the default value of zero might be wrong, so add a FIXME comment. Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22mb/google/kukui: revise config structure for Jacuzzi followersHung-Te Lin
There are more Jacuzzi followers coming and we want to have a simplified way of adding new boards. Now, detachable and tablets should select BOARD_GOOGLE_KUKUI_COMMON and clamshells should select BOARD_GOOGLE_JACUZZI_COMMON. BUG=None TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper BRANCH=kukui Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-21mb/google/dedede: Create madoo variantIan Feng
Create the madoo variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:161191394 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_MADOO Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-21soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik
This patch performs below operations 1. Add support for FSP 2.2 2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call FspMultiPhaseSiInit() API. 3. Provide placeholder to perform require chipset programming (example TCSS) before calling FspMultiPhaseSiInit() API. Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-21mb/googlz/zork: Drop unnecessary PULL_UPs in variant overridesFurquan Shaikh
This change drops the pulls configured on override GPIOs as they already have external pull-ups. Also, pads which are unused are configured as PAD_NC. BUG=b:154351731 Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-21sb/intel/lynxpoint/me_9.x.c: Add spaces around `=`Angel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I1baa731335a9c543c7d31b9aadc8758806750c64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42629 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21mb/system76/lemp9: drop FSP_M_XIPMichael Niewöhner
Drop FSP_M_XIP since it's selected by the soc already. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-07-21mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARYMichael Niewöhner
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards with multiple graphics devices. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21mb/lenovo/t430/gma-mainboard.ads: Replace with GPLv2+ equivalentPeter Lemenkov
Replace it with t430s/gma-mainboard.ads which is licensed under more flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I633702d363134654e71e35404237d75b499f089a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21mb/lenovo/t420/gma-mainboard.ads: Replace with GPLv2+ equivalentPeter Lemenkov
Replace it with t420s/gma-mainboard.ads which is licensed under more flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I5393a603b5a4cd353149c1fa9e3e29020946b962 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21security/intel/stm: Add missing <stdbool.h>Angel Pons
Jenkins does not build `config.stm` because the file name lacks the mainboard name. So, the code was not being build-tested, and it does not build because several files lacked the definition for `bool`. Add the missing #include directives. Renaming the config file so that Jenkins build-tests it is done in a follow-up. Change-Id: Idf012b7ace0648027ef6e901d821ca6682cee198 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43622 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21src: Use ACPI macrosElyes HAOUAS
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21soc/intel/baytrail: Add new CPUID 0x30679Mate Kukri
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards. Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21mb/biostar: Add TH61-ITX portMate Kukri
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge) - RAM: native raminit tested (4G+4G, 8G+8G) - USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4) - LAN: tested in Linux - SATA: all 4 ports work, tested in SeaBIOS and Linux - iGPU: I can't test it as I only have a Xeon for this socket - PEG: tested with an nVidia GT210, initialized by SeaBIOS - PS2 keyboard and mouse combo port: no devices to test with - Front panel header: tested, works - Audio: tested, works - Diagnostic LEDs: TBD Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21e7505/i82801dx: Use common code for early SMBusAngel Pons
While it looks different, the early SMBus code for this southbridge is still the same. In addition, this code was not checking the vendor ID before. It is assumed that adding this check does not pose a problem. Change-Id: I95ae4db399ce5592cefca82fa75f349220023b8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42006 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21i945/pineview/x4x/i82801gx: Use common code for early SMBusAngel Pons
The early SMBus code for this southbridge checked if the PCI device ID is valid. However, we can't easily do that in common code, and we should not attempt to do so either: if a SMBus device behaves differently, then it should not be using the common code anyway. Since this southbridge is used with two different northbridges, we need to update both of them. Plus, x4x raminit no longer needs to know which southbridge it is paired with, since both i82801gx and i82801jx use the common early SMBus code, so we drop some preprocessor around includes. Change-Id: Ic60a3f89bda6000fbe646461f05240c1b09db6e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42005 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21gm45/i82801ix: Use common code for early SMBusAngel Pons
The early SMBus code for this southbridge checked if the PCI device ID is valid. However, we can't easily do that in common code, and we should not attempt to do so either: if a SMBus device behaves differently, then it should not be using the common code anyway. Change-Id: I5c21e091e437d23a173ddcf35d4f1efada6194cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42004 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21x4x/i82801jx: Use common code for early SMBusAngel Pons
The early SMBus code for this chipset was not checking the vendor ID before. It is assumed that adding this check does not pose a problem. Change-Id: I0c36c8cd8aca8db860b1edafd29d4f2dbaa2c822 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42003 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21sb/intel/lynxpoint: Use common code for early SMBusAngel Pons
Looks like no one uses early SMBus for now, but that may change someday. Change-Id: I42971662a279860a8c2e058fcb194fe5eba7c740 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42001 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21sandybridge/bd82x6x: Use common code for early SMBusAngel Pons
Change-Id: I95b82f3d733db2a46096205f23ed85aaff021e28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42000 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21ironlake/ibexpeak: Move early_smbus.c to common codeAngel Pons
We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21device/cardbus_device.c: Drop `cardbus_size_bridge_resource`Angel Pons
It does nothing useful anymore. Drop it before it grows moss. Change-Id: I5f95376fe2a38eda5d819c53edb85ef11ab7a0f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43591 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21soc/intel/xeon_sp/cpx: remove unused gpio.hMaxim Polyakov
This file does not contain useful information and is not used to build the image. The common GPIO driver from soc/intel/common uses layout in lewisburg_pch_gpio_defs.h [1,2] file, which is correct for all chipsets from the Lewisburg family: C621, C621A, C622, C624, C625, C626, C627, C627A, C628, C629, C629A [3] [1] src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h [2] https://review.coreboot.org/c/coreboot/+/39425 [3] Intel document #547817 Change-Id: I1f3ac4afff9e628890df8cec075fd3e42a590172 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43535 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20google/trogdor: Remove write_protect_stateEric Lai
This is no longer used for chromeos.c. BUG=b:160752610 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a716a88ff9811fff46abca229be15522733bfef Reviewed-on: https://review.coreboot.org/c/coreboot/+/43472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-20drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring strapsAngel Pons
Unconditionally selecting `GFX_GMA_IGNORE_PRESENCE_STRAPS` creates a hard dependency on `MAINBOARD_USE_LIBGFXINIT`, which is undesired. Move it out of the `if GFX_GMA` block to break this unwanted dependency. TEST=Build for Librem 13v4 with no graphics init successfully. Change-Id: I53e132c209c065068f20959fa1a6f5195f5fe766 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20mb/google/dedede: Update link frequency and end point structure for OV9734Pandya, Varshit B
1. Update Link frequency to 180 Mhz 2. Set data-lanes to 1 and 3. Update the clock-lane used by sensor BUG=b:155285666 BRANCH=None TEST=Build and able to capture image using user facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20mb/amd/mandolin: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for dalboz referenceFurquan Shaikh
This change drops internal pulls for dalboz reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP1800_S0 GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_32: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for trembyle referenceFurquan Shaikh
This change drops internal pulls for trembyle reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP3300_A GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_90: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Report word-sized access for PM1a_EVTAngel Pons
According to the ACPI specification, version 6.3: Accesses to the PM1 status registers are done through byte or word accesses. The same is said about the PM1 Enable registers. Therefore, reporting dword-sized access is wrong and means nothing anyway. Since some other platforms use word-sized access, use word everywhere for consistency. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel/i82801dx/fadt.c: Use ACPI_ADDRESS_SPACE_IOAngel Pons
Tested with BUILD_TIMELESS=1, AOpen DXPL Plus-U remains identical. Change-Id: I80ec4d0d6a8ec0dc02b377cfa3f3b5f0362dbb6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-20sb/intel/bd82x6x/fadt.c: Use definitions instead of numbersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I2212a6dd4b02ac8fdcf1eafbab0226ad9faa825e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-20sb/intel/ibexpeak/fadt.c: Use definitions instead of numbersAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: If0ee1b65a1be67ee9f5f832f076c365017a14e6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20soc/amd/stoneyridge: Select HAVE_CF9_RESETAngel Pons
Looks like some preparation is needed before reset. However, Picasso also needs some special handling and still selects this option without selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now. Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
Instead, just flip the desired bits using bitwise operations. As this is initially zero, the resulting value is the same. This allows flags to be set from anywhere regardless of execution order. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20soc/intel/xeon_sp/skx: Clean up FADTAngel Pons
Both `acpi_fill_fadt` and `soc_fill_fadt` set many FADT fields. Since the latter runs later, the values programmed in it overwrite any other values. Drop unused assignments and consolidate everything in a single function. Use `acpi_fill_fadt` as it is mandatory (no weak definition). Change-Id: Ia8248f20dae2b93426f309605bb2076592b08df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43386 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel/i82371eb: Declare reset register in FADTAngel Pons
According to Intel Order Number 290562 (PIIX4 datasheet), 0xcf9 is the reset register, and setting bits 1 and 2 will result in a hard reset. Change-Id: Id5ada6a10b2269d51908c6a5fd7745ef6c33a29a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20sb/intel/i82801dx: Declare reset register in FADTAngel Pons
According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset register, and setting bits 1 and 2 will result in a hard reset. Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20sb/intel/i82801dx: Drop unneeded PM2 settings from FADTAngel Pons
The PM2_CNT register block is not present on this southbridge, as per Intel Document 290744 (ICH4 datasheet). Also, the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register), says: This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Also delete a comment about `pm2_cnt_len`, which said that the right value differs from zero. Looks like that comment was wrong instead. Change-Id: Icbb32f5db7b368c764b3477c40f8ae9c788df5ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43383 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel/i82371eb: Drop unneeded PM2 settings from FADTAngel Pons
The PM2_CNT register block is not present on this southbridge, according to comments on the code. As per the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register): This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Change-Id: Ib3ff0fd9e0725f61c38e60ba56b95e6e77b0b1ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43382 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20amd/{hudson,stoney,picasso}: Drop PM2 settings from FADTAngel Pons
The PM2_CNT register block is no longer needed, as explained in some comments. While they may have been copy-pasted around a lot, they are at least true for Hudson, and it makes sense to assume that they are true for newer chipsets as well. As per the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register): This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless PM1b settings from FADTAngel Pons
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event register blocks. According to the ACPI specification, version 6.3, sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers): If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with PM1b for now. So, drop unneeded writes to PM1b fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless GPE1 settings from FADTAngel Pons
None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-20soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settingsJamie Chen
Add configs for USB 3.1 Gen2 EV settings so that people can set the EV settings per board in device tree. BUG=b:150515720 BRANCH=none TEST=build coreboot and fsp with enabled fw_debug. Flashed to puff and checked the log. All usb configs were set correctly. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: Id4860665619095139c329565d433d9eb495cac02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/asrock/b85m_pro4: Enable VGA portAngel Pons
Now that libgfxinit has been fixed, trying to enable the Analog port no longer hangs the system, nor fills the monitor with unreadable garbage. Tested with linear framebuffer, displays correctly on a 1920x1080 VGA monitor. Scaling also works when a smaller HDMI monitor is connected as well. Legacy VGA text mode is also functional on either monitor, too. Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:12:02 +0000