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2017-06-14mainboard/google/{poppy,soraka}: Disable unused GSPI1 interfaceFurquan Shaikh
TEST=Verified that board still boots to OS without any error. Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI nodeFurquan Shaikh
Now that we dynamically disable TPM interface based on config options, add support for generation of SPI TPM ACPI node if SPI TPM is used. Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-14mainboard/google/poppy: Disable unused TPM interface dynamicallyFurquan Shaikh
Based on the config options selected, decide at runtime which TPM interface should be disabled so that ACPI tables are not generated for that interface. TEST=Verified that unused interface does not show up in ACPI tables. Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20141 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add missing PCH_DEV_* definitionsFurquan Shaikh
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14soc/intel/common/block/i2c: Ignore disabled I2C devicesFurquan Shaikh
If I2C device is disabled: 1. BAR for the device will be 0 2. There is no need to generate ACPI tables for the device TEST=Verified that if an i2c device is disabled statically in devicetree or dynamically in mainboard, then coreboot does not die looking for missing resources. Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14Add support for Undefined Behavior SanitizerRyan Salsamendi
Initial support for undefined behavior sanitizer in ramstage. Enabling this will add -fsanitize=undefined to the compiler command line and link with ubsan.c in ramstage. Code with UB triggers a report with error, file, and line number, then aborts. Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-14cbmem_console: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Left shifting an int where the right operand is >= width of type is undefined. Add ul suffix since it's safe for unsigned types. Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-14arch/x86: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other write16()s in setup_ebda() to memcpy() for consistency. Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-13nb/intel/pineview/raminit.c: Use static const for lookup tablesArthur Heymans
Also changes the arguments of some functions to const. This reduces romstage size by a whopping 1009 bytes. Change-Id: I054504412524b7be19d98081097843b61bc0c459 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-13cpu/x86/mtrr: fail early if solution exceeds available MTRRsAaron Durbin
If an MTRR solution exceeds the number of available MTRRs don't attempt to commit the result. It will just GP fault with the MSR write to an invalid MSR address. Change-Id: I5c4912d5244526544c299c3953bca1bf884b34d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20163 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-13cpu/amd/fam10/ram_calc: Remove superfluous guardArthur Heymans
AMD_FAM10H code enables early cbmem by default. Change-Id: Ifad007f6604bb612d544cf1387938a8fef1cceb4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-13siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
Since this mainboard provides 3 COM ports on LPC, enable decoding of the corresponding address range for COM 3. Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-13siemens/mc_apl1: Use Siemens NC FPGA driverMario Scheithauer
- use Siemens NC FPGA driver for backlight brightness and PWM control - set Dsave time for board reset after falling edge of signal xdsave Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-13siemens/nc_fpga: Expand FPGA functionalityMario Scheithauer
The siemens/mc_apl1 mainboard needs more functionality provided by Siemens NC FPGA. The additional functionality contains backlight brightness/PWM control and Dsave time for board reset. Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-13vendorcode/siemens: Add new values to hwilibMario Scheithauer
The Siemens mc_apl1 mainboard needs new values from hwilib. - add Dsave time for board reset - add backlight brightness for panel setting - add backlight PWM period Change-Id: I3a48654ef57c7f8accaabe60e8aec144e4fe5466 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12nb/intel/gm45: Add romstage timestampsArthur Heymans
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12nb/intel/ivybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12nb/intel/sandybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12src/cpu/amd/model_fxx/powernow_api.c Fix checkpatch errors + warningsEvelyn Huang
Fix line over 80 characters, spaces required around comparisons,space required after close brace '}', comma ',', semicolon ';', space prohibited after ')' errors and warnings Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-12mb/foxconn/g41s-k: add new mainboardSamuel Holland
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O. Tested, working: * Booting Linux 4.11.3 and Windows 8.1 from USB and HDD * Resume from S3 (Linux and Windows) * Native raminit (DDR2-800) * Native graphics init (SeaBIOS, Linux) * Graphics init with VGA BIOS (SeaBIOS, Windows) * PCI-E x16 PEG slot, PCI-E x1 slot from southbridge * Realtek ALC888 HD Audio (including front panel and jack detection) * Realtek R8168 Gigabit LAN * Both SATA ports * USB 1.1 and 2.0 devices (keyboard, mass storage) * PC speaker beep * COM header * Super I/O Environment controller (temps, voltage, fans) * PS/2 keyboard and mouse * Flashing with `flashrom -p internal` * 1MiB and 2MiB SPI flash chips * CMOS gfx_uma_size Appears, OS driver loads, but otherwise untested: * IrDA header * CIR header * TPM header Untested: * S/PDIF digital audio Tested, known broken: * CMOS power_on_after_fail * USB keyboard in secondary payloads Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20027 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-12ec/librem/ec: Fix offset for Bluetooth enable (BTLE)Matt DeVillier
Test: boot OS (Ubuntu, Windows 10) on librem13v2, verify BT function key toggle now works correctly. Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-12mb/emulation/spike-riscv: Update UART addressJonathan Neuschäfer
I updated my spike patch[1] to cleanly apply to current spike master. As a side effect, the UART is now at 0x02100000. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I4cb09014619e230011486fa57636abe183baa4be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/20126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-06-12src/cpu/amd/atrr/amd_mtrr.c Fix checkpatch errors + warningsEvelyn Huang
Fix line over 80 characters, unnecessary braces for single statement blocks, spaces before close parantheses errors and warnings. Signed-off-by: Evelyn Huang <evhuang@google.com> Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d Reviewed-on: https://review.coreboot.org/20097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-12src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errorsEvelyn Huang
Fix space prohibited between function name and open parenthesis, line over 80 characters, unnecessary braces for single statement blocks, space required before open brace errors and warnings Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12src/console: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I5a674cd7a360a0dd040c859ec1f8d760d7c83364 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-12cpu/x86: fix spelling mistakeMartin Roth
Change-Id: Id88455f2c7c28e0b298675b9af2a39361759a34a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19120 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12src/drivers: Add license headersMartin Roth
Change-Id: I1c4b30ab47e12ec35cb681ec5c6635ecd20aa2e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19121 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12soc/baytrail: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for google/rambi as to not break compilation. Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12superio/ite/it8720f: add new IT8720F Super I/OSamuel Holland
This device is extremely similar to the IT8718F, so support is based on existing support for the IT8718F. The CIR device is only detected by Linux/Windows from the ACPI tables, so ACPI support is extended from the IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K. Tested, working: * Serial port 1 * Environment controller - Temperature monitoring - Voltage monitoring - Fan control (automatic and manual) * PS/2 keyboard and mouse Appears, OS driver loads, but otherwise untested: * Serial port 2 * Consumer IR Untested: * Floppy controller * Parallel port * GPIO Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/ite/it8728f: remove unused headerSamuel Holland
Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/ite/common: fix prototype to match othersSamuel Holland
Change-Id: Id4a079d868c5c806c769b5559833566e8a6a8a71 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/acpi: allow custom HID on generic deviceSamuel Holland
Some Super I/O PnP devices are detected by string matching the hardware ID. Allow providing a custom HID to override the default generic one. Change-Id: I7793b7d53c9d94667675f9dee63358521ac8c4be Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/acpi: allow 3 I/O ranges on generic deviceSamuel Holland
Some Super I/O logical devices have three I/O port ranges, such as the GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix a typo in the I/O range description. Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-09elog: Add more detailed wake source events for USB2.0/3.0 port wakeFurquan Shaikh
BUG=b:37088992 Change-Id: If0b495234d6e498d5c64ba4dd186440cd7a1c5c6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09lib/spd_bin: Print out correct SMBus SPD address in dump_spd_infoFurquan Shaikh
With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an input), SMBus SPD addresses are accepted from the mainboard and not calculated within the spd_bin library routines. Use the addr_map values to print correct address in dump_spd_info. Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/intel/apollolake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09mb/asrock/g41c-gs: Rename the board to G41C-GS R2.0 (g41c-gs_r2_0).Bill XIE
The supported "G41C-GS" with a nuvoton nct6776 superio is actually G41C-GS R2.0, which is different with the more easily-found revision G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported separately. Photos for the two revision: R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-09soc/intel/apollolake: Rename ACPI Base Address and Size MacroBarnali Sarkar
Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Enable ACPI PM timer emulation on all CPUsSubrata Banik
This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/common/block: Add Intel common CPU library codeBarnali Sarkar
Create Intel Common CPU library code which provides various CPU related APIs. This patch adds cpulib.c file which contains various helper functions to address different CPU functionalities like - cpu_set_max_ratio(), cpu_get_flex_ratio(), cpu_set_flex_ratio(), cpu_get_tdp_nominal_ratio(), cpu_config_tdp_levels(), cpu_set_p_state_to_turbo_ratio(), cpu_set_p_state_to_nominal_tdp_ratio(), cpu_set_p_state_to_max_non_turbo_ratio(), cpu_get_burst_mode_state(), cpu_enable_burst_mode(), cpu_disable_burst_mode(), cpu_enable_eist(), cpu_disable_eist(), cpu_enable_untrusted_mode() Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/apollolake: Perform CPU MP Init before FSP-S InitBarnali Sarkar
As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=none BRANCH=none TEST=Build and boot Reef Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20037 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/apollolake: Remove duplication of find_microcode_patch() codeBarnali Sarkar
Since get_microcode_info() is aleady searching for the microcode in cbfs, we can just add a intel_microcode_load_unlocked() call here to update the microcode. No need to duplicate finding microcode step during pre_mp_init() function. Change-Id: I525cab0ecc7826554f0a1209862e6357d1c7a9a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar
FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in get_microcode_info callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/apollolake: use fast_spi_cache_bios_region()Aaron Durbin
The fast_spi_cache_bios_region() does the necessary lookup of BIOS region size, etc. Don't inline the calculation and just defer to the common piece of code for memory-mapped spi flash boot. Change-Id: I6c390aa5a57244308016cd59679d8c3ab02031b8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09soc/intel/common/fast_spi: support caching bios in ramstageAaron Durbin
After the MTRR solution has been calculated provide a way for code to call the same function, fast_spi_cache_bios_region(), in all stages. This is accomplished by using the ramstage temporary MTRR support. Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20115 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 02:46:26 +0000