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2013-11-24Honor vboot's request to load the VGA option ROMBill Richardson
This removes an earlier patch that caused the VGA option ROM to be loaded by coreboot even in normal mode when it isn't needed. Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48173 Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4125 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Northbridge: i945: Native VGA init: print the GMA and GTT addressesPeter Stuge
The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Northbridge: i945: Native VGA init: use UMA addressPeter Stuge
The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Lenovo X60: Native VGA init: Get rid of the memory corruptions.Peter Stuge
Without that fix the GTT points at 0x00000000. The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24lenovo/x60: native vga init: fix code style issues.Denis 'GNUtoo' Carikli
Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3999 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24dmp/vortex86ex: Move DMP specific POST code defines into one fileAndrew Wu
Move into src/cpu/dmp/dmp_post_code.h Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24lenovo/x60: export reboot_bits nvram configuration.Denis 'GNUtoo' Carikli
This permits any software running after the ramstage to tell coreboot that the boot was successfull. Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3992 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24haswell: Put each logical processor in its own P-state domainDuncan Laurie
The recommendation from Intel is to report each core as a separate logical domain in the _PSD table. This goes against the recommendation in the ACPI specification because all of these cores are on the same package and share a VR so they will do voltage transitions together. The reasoning is that with a larger number of logical processors the P-state often ramps too quickly resulting in higher power consumption. By exposing each core as a separate domain the OS can manage them individually allowing the socket to select the optimum frequency. $ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT $ iasl -d /tmp/SSDT Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000001, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000002, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000003, 0x000000FE, 0x00000001 } }) } Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24haswell: Update microcode for ULT/40651 to rev 8Duncan Laurie
$ cat /sys/devices/system/cpu/cpu*/microcode/version 0x8 0x8 0x8 0x8 Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4129 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Fix compile error in chromeos by adding stddef.hDuncan Laurie
Compile was failing with the following error: In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0, from src/vendorcode/google/chromeos/chromeos.c:22: vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t' src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload': src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function) Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48289 Reviewed-on: http://review.coreboot.org/4131 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Lenovo hotkeys supportVladimir Serbinenko
Implement proprietary lenovo ACPI hotkeys Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4055 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23Change EC GPE on X201Vladimir Serbinenko
X201 has GPE at 0x11 (17) instead of 28. Tested on X201. Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4053 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23lib/coreboot_table: set type and size of framebuffer tag after ↵Vladimir Serbinenko
fill_lb_framebuffer When testing Ron's patch on qemu I found out that fill_lb_framebuffer overwrites size and tag fields. We need either to fix/check all fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer. I prefer later as it's more robust. Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4263 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.Vladimir Serbinenko
2065x is with nehalem and not sandybridge. I don't care much eitherway but it clears some confusion. Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4046 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-23Call X201 dock hooks in EC codeVladimir Serbinenko
Unlike on X60/T60 dock has to be inited at the same time as EC. Change-Id: If6eb3140c871859ce99027a50908f72bcc560243 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4082 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-23Remove MRC variables from 2065x CAR init.Vladimir Serbinenko
2065x boards don't use MRC. And the space in question isn't used either. Read number of variable range MTRRs from MSR rather than hardcoding it. 2ff is still zeroed out as unless you zero-out undocumented bits as well boot fails. Tested on Lenovo X201. Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4080 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-11-22Don't wait on 2065xVladimir Serbinenko
The mdelay is not necessarry on 2065x. Tested on X201 that it works without delay. Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4083 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-11-22AMD f15tn, f16kb: Remove CDIT table and DMI tableWANG Siyuan
On AMD Trinity and Kabini boards errors similar to the following are shown. ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431 DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 The reason is that on f16kb boards, the CDIT and DMI table are not created. On f15tn boards, only the DMI table is not created. Until the root cause is found, disable the table generation to remove the errors. Thanks to Wei Hu for debugging and reporting this issue on the list [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html CDIT table is not created Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4092 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-21Fix error message on wrong compiles of 2065xVladimir Serbinenko
Current error message refers to sandybridge chipset. Instead error should be that 2065x needs Ibex Peak. Change-Id: I8cc8a34f496aec7af0ce95b4b65fd25e165f43fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4202 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19Asus F2A85-M: Fix S3 memory power cut-offRudolf Marek
The power to memory is lost during the the suspend, activate the 3VSBSW# which switches the power during S3 suspend sequence. As a result resuming from suspend to RAM works now, but now the GPP ports of the Hudson southbridge are gone after resume from S3. The devices 15.0 and 15.1 are disabled (decode as ffff) and therefore anything behind them too [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html fam15tn hudson PCIe GPP ports off after resume Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/4041 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-19Add GRUB2 payload to build systemVladimir Serbinenko
Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and FILO. So make it easy for coreboot users to use GRUB 2 as a payload by integrating it into coreboot’s build system, so it can be selected in Kconfig. As the last GRUB 2 release 2.00 is too old and has several bugs when used as a coreboot payload only allow to build GRUB 2 master until a new GRUB release is done. The downside is, that accidental breakage in GRUB’s upstream does not affect coreboot users. Currently the GRUB 2 payload is built with the default modules which results in an uncompressed size of around 730 kB. Compressed it has a size of 340 kB, so it should be useable with 512 kB flash ROMs. Tested with QEMU. Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4058 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-18cbfs: 64-bit cleanupsRonald G. Minnich
cbfs used u32 in a number of cases where uintptr_t was correct. This change builds for both 64-bit and 32-bit boards. Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4037 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18cbfs: remove unused code and prototypeRonald G. Minnich
The code is wrong (it's calling ntohl on an entry point that is actually already le due to an old cbfs bug) and nothing calls it any more anyway. Change-Id: Ief2c33faf99e3d2fc410524a5aae7bde378f088b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4090 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18qemu: set smbios entries from fw_cfgGerd Hoffmann
Qemu makes the guest uuid (qemu -uuid $uuid) available to the guest via fw_cfg. Other smbios fields can be configured in qemu using the -smbios command line switch (check the qemu manpage for details). This patch adds coreboot support for this, so the values provided by qemu will actually show up in the smbios table. Change-Id: Ifd9ae0d02749af4e7070a65eadbd1a9585a8a8e6 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-18smbios: make manufacturer, product_name and uuid runtime settableGerd Hoffmann
Make manufacturer, product_name and uuid smbios fields (type 1) configurable at runtime, simliar to version and serial number. Change-Id: Ibc826225e31fa42aa944fa43632dd6a406d5c85d Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4085 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-15qemu: load acpi tables from fw_cfg.Gerd Hoffmann
Starting with release 1.7 qemu provides acpi tables via fw_cfg. Main advantage is that new (virtual) hardware which needs acpi support JustWorks[tm] without having to patch & update the firmware (seabios, coreboot, ...) accordingly. So if we find acpi tables in fw_cfg try loading them, otherwise fallback to the builtin acpi tables. Change-Id: I792232829b870ff6ed8414a3007e0af17f6c4223 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4040 Tested-by: build bot (Jenkins)
2013-11-15Lenovo T60/X60: cmos.layout: Replace tabulators with spaces for consistencyPaul Menzel
Change-Id: Iec0abae8a4b18ac737e9ebb3eac219182729be0f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4057 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-13intel/2065x: Use TSC for udelay()Vladimir Serbinenko
For the ram init of Intel Nehalem ram init we need a udelay implementation. Use common TSC framework for it as Intel Haswell already does. Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4043 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-11-11qemu: load e820 from fw_cfgGerd Hoffmann
qemu 1.7+ provides a fw_cfg file named "etc/e820" with e820-like entries for reservations and ram regions. Use it for ram detection if present, otherwise fallback to the traditional cmos method. Change-Id: Icac6c99d2a053e59dfdd28e48d1ceb3d56a61bdc Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4030 Tested-by: build bot (Jenkins)
2013-11-11qemu: add fw_cfg files supportGerd Hoffmann
Qemu can provide files using the firmware config interface. This is used to pass config options, virtual machine config info and option roms into the guest. This patch adds support for reading the file index and loading files from qemu. Change-Id: I57d4a734527c4117239f355121cf1fb8a390ab0d Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4029 Tested-by: build bot (Jenkins)
2013-11-10add memory clobber to ins{b,w,l}Gerd Hoffmann
Change-Id: Ia710eb59f23a52afba2a8ef6e0ff2b2306107245 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-11-10sio1007: Properly build '.c' filesMarc Jones
Properly build the super i/o .c files. This prevents including the .c file directly in romstage, which is generally bad practice. Adding a Makefile and a .h file to include. Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4014 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-10emeraldlake2: Clean up COM port enableMarc Jones
Remove the COM port enable loop. There is no need to search for the port when it is needed and known by the GPIO function. Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-10console: Add hexdump32 functionMarc Jones
Add a function to display memory locations in the console logfile. Change-Id: Iddb8d2e7a24357075f32c2fdf7916ae7a732247d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-08Add new finalize functions for devices and chipsMarc Jones
Many chipset devices require additional configuration after device init. It is not uncommmon for a device early in the devicetree list to need to change a setting after a device later in the tree does PCI init. A final function call has been added to device ops to handle this case. It is called prior to coreboot table setup. Another problem that is often seen is that the chipset or mainboard need to do some final cleanup just before loading the OS. The chip finalize has been added for this case. It is call after all coreboot tables are setup and the payload is ready to be called. Similar functionality could be implemented with the hardwaremain states, but those don't fit well in the device tree function pointer structure and should be used sparingly. Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4012 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16`Paul Menzel
Change-Id: Id4a758644a7b799e7662113c07d395e053525934 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`Paul Menzel
Change-Id: I6bb652419a54b7b7190e417346581f38335425ae Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05usbdebug: Fix build for ROMCC boardsKyösti Mälkki
Header file is not compatible with romcc, just drop it as a romstage built with romcc cannot use usbdebug anyway. Change-Id: If7f8f22d6a8fa1f02157df281f82f02b72b6a609 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4006 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-30southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`Paul Menzel
Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail with the following error. src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic': src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Removing `dummy` should be safe as GCC probably optimizes it away before anyway. That no dummy variable is used for an RCBA [1] access in Intel Lynx Point supports that this can be dropped safely. [1] root complex base address [2] src/southbridge/intel/lynxpoint/early_pch.c Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3982 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-22vortex86ex: Defer checking PS/2 keyboard controller system flagAndrew Wu
Don't check keyboard controller system flag until before calling pc_keyboard_init(). This makes waiting time shorter. Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3958 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-22usbdebug: Fix boards without EARLY_CBMEM_INITKyösti Mälkki
The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-19winent-mb6047: initial WIN Enterprises MB-60470 board portJonathan A. Kollasch
What works: - ACPI interrupt routing for onboard devices - onboard devices including USBs, ATAs, NICs, COM1 What almost works: - SMI720 VGA BIOS needs forthcoming VGA BIOS hooks in SeaBIOS to work Untested: - Interrupt Line Register interrupt routing - PIRQ interrupt routing - MPBIOS/MPTABLE interrupt routing - unpopulated on board revision 1A AC97 audio - unpopulated PCI-E x16 slot - unpopulated ExpressCard slot - HT expansion board Thanks to WIN Enterprises for providing boards. Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3975 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-10-19winent-mb6047: copy tyan/s2891 mainboard directoryJonathan A. Kollasch
Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3974 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-18get_bus_conf.c: reindent with indentPaul Menzel
Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3979 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-10-17arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOSAndrew Wu
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3896 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-15CBMEM: Define cbmem_top() just once for x86Kyösti Mälkki
It is expected this will always be a casted get_top_of_ram() call on x86, no reason to do that under chipset. Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3972 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15Have option of timestamps, CBMEM console and usbdebug for most boardsKyösti Mälkki
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage, and have no CAR migration, these features are available for ramstage only. Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15CBMEM: Fail builds on missing get_top_of_ram()Kyösti Mälkki
Dummy get_top_of_ram() is removed from romstage to fail already at build-time for cases where cbmem_initialize() would not complete. The mechanisms behind CAR_GLOBAL migration only work correctly when romstage can succesfully make the cbmem_initialize() call. Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15intel/i82371: Remove HAVE_ACPI_RESUMEKyösti Mälkki
This is needed to apply a rule that get_top_of_ram() in romstage is required to select HAVE_ACPI_RESUME, otherwise chipset/board has no means to backup low memory to CBMEM on s3 resume. Only board affected is asus/p2b. Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3971 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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