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2018-09-13uart/sifive: make divisor configurablePhilipp Hug
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-13src/mainboard/*/*: Set Mini-ITX boards' category to "mini"Angel Pons
Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel: introduce warning when building with no IFDAngel Pons
Add a warning as suggested in patch CB:28233 with the "CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option. Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12soc/sifive/fu540: Initialize PLL and clockPhilipp Hug
Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12soc/amd/stoneyridge: Fix more GPIO functionsJonathan Neuschäfer
Instead of gpio_num, gpio_address should be used as the address in write32. This lets us also get rid of a few casts. Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed one instance of this bug, but it was more widespread. TEST=None Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-11amd/stoneyridge: Enable BERT table generationMarshall Dawson
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional help text. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-11amd/stoneyridge: Set BERT region size when no TSEG usedMarshall Dawson
Expand the BERT reserved region size setting to account for the possibility of no TSEG configuration. This change is only for completeness, as stoneyridge must always use TSEG. Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-11soc/intel/baytrail: Remove trailing space in log messagePaul Menzel
Currently, there is a trailing space in the log message below. > Enabling VR PS2 mode: VNN VCC So, put the space before the word. Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-11src/device/dram: Fix typoElyes HAOUAS
Change-Id: I5d8e5f978c538d2b9f74b29e21eb39ce6455315f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-10soc/sifive: fix compiler warningPhilipp Hug
Fix the following compiler warning on the latest toolchain: src/soc/sifive/fu540/otp.c:48:1: error: useless storage class specifier in empty declaration [-Werror] } __packed; ^ Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28553 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-10soc/sifive/fu540: Makefile: include mtime_init in ramstagePhilipp Hug
Fix compilation issue clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28551 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10soc/sifive/fu540: Add driver for OTP memoryPhilipp Hug
Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10mainboard/google/poppy/variants/rammus: Enable DA7219marxwang
On rammus, headset uses DA7219 so that we need to enable it. BUG=b:112945714 BRANCH=master TEST=emerge-rammus coreboot chromeos-bootimage Flash FW and check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28537 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10soc/intel/cannonlake: Correct number of root ports for CNL PCH HMaulik V Vaghela
CNL PCH H supports maximum 24 root ports while CNL PCH LP supports maximum 16 root ports. Change-Id: I2cc3ae282d4eb5da8b0618451e062a6c061f1d6f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/28399 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10soc/sifive/fu540: add CLINT supportXiang Wang
Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10riscv: update mtime initializationXiang Wang
Add a interface, which is implemented by SoC. Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10complier.h: add __noreturn and use it in code baseAaron Durbin
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace current users with the macro. Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-10mb/google/poppy: Set UPD CmdTriStateDis for NocturneShaunak Saha
This patch sets the MRC UPD CmdTriStateDis for the nocturne boards.Nocturne is LPDDR3 design without RTT for CMD/CTRL. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: I0f593761dcbd121e7e758421af178931b9d78295 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28379 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetreeShaunak Saha
This patch adds the support for CmdTriStateDis FSP upd in skylake soc structure so that we can define it in devicetree.CmdTriStateDis needed to be set for the skylake/kabylake based boards where LPDDR3 design is without RTT for CMD/CTRL.We need to set this bit for those designs for the margin to be proper. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09drivers/vpd: Add VPD supportPatrick Rudolph
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md Copy ChromeOS VPD driver to add support for VPD without CROMEOS. Possible use case: * Storing calibration data * Storing MAC address * Storing serial * Storing boot options + Now it's possible to define the VPD space by choosing one of the following enums: VPD_ANY, VPD_RW, VPD_RO. + CHROMEOS selects now VPD as part of it. + VPD is implemented as driver. Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09mainboard/google/kahlee: Reset trackpad & touchscreenMartin Roth
AMD chips don't hold off a reset to the end of I2C transitions, so devices on the i2c bus can be left in a bad state. To avoid this, make sure the trackpad and touchscreen chips get disabled during boot. BUG=b:114411165 TEST=build, reboot watch trackpad enable go low Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07mb/google/poppy/variants/atlas: enable NVMeCaveh Jalali
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-07lib/gpio.c: Fix _gpio_base3_value invalid shiftRichard Spiegel
Coverity CID 1395334: (BAD_SHIFT) - In function _gpio_base3_value(), if gpio_num is 32 and gpio[31] is floating, the end result is 1 << 32, which does not fit into a int. To avoid a possible error, make it an error to have num_gpio > 31. Function _gpio_base2_value also have the same issue, but the limit would be 32. As in practice it'll never be used with more than 20 GPIO, create a helper function to limit it to 31 and call it everywhere needed. BUG=b:113788440 TEST=Add a fake code to southbridge_final calling the function and printing the result. Build and boot grunt, check result. Change-Id: I0b79725bcbaf120587c7440e176643aaa7a1d5bb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28445 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Construct ACPI BERT tableMarshall Dawson
Add a Boot Error Record Table to the ACPI information. Avoid a driver error message by skipping the table altogether when no errors are found, or support isn't built in. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28478 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Construct BERT region from machine checkMarshall Dawson
Add functions to build a Boot Error Record Table region based on settings found in the MCA registers. Two entries are reported for each error due to the nature of the ACPI driver. The first is a Generic Processor Error, which the OS recognizes and parses. Generic errors cannot convey much error description or processor context. Therefore an IA32/X64 Processor Error is also added, which allows reporting the values found in the MCA MSR registers. Follow-on work could decode the MC errors more precisely, and better completing the Generic Error and the Check structure. The current level of support is sufficient to identify a (i.e., human readable) problem in dmesg, and provides adequate context information for analysis. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28477 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Create an MCA structureMarshall Dawson
Convert the Machine Check reporting to use a newly defined structure. This will facilitate later patches that will pass pointers to the MSR values. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28476 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Relocate MCA error identificationMarshall Dawson
Move the process of interrogating the Machine Check registers into its own file. This rearranges source code in preparation of supporting a Boot Error Record Table, which stoneyridge will use to report latent MC errors to the OS. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07amd/stoneyridge: Adjust memory map for reservedMarshall Dawson
Carve out memory to be reported to the OS as reserved. This makes room for a region usable for Boot Error Record Table information. The BERT region reserved size is larger than likely requried, however the SMM region's base must be on a boundary matching the granularity of its size. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28474 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/fam15: Add more MCA informationMarshall Dawson
Add more definitions to be used for Machine Check Architecture support, mainly for determining the type of error that is being interpreted. MCA is described in detail in the BKDG. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07x86/acpi: Add BERT tableMarshall Dawson
Create a structure for the Boot Error Record Table, and a generic table generator function. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07x86/acpi: Add BERT to the revision tableMarshall Dawson
Add the proper table revision level for the Boot Error Record Table. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28471 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07arch/x86: Add BERT region support functionsMarshall Dawson
Add code for generating the region pointed to in an ACPI Boot Error Record Table. The BERT region must be reported as Reserved to the OSPM, so this code calls out to a system-specific region locator. cbmem is reported as type 16 and is not usable for the BERT region. Events reported via BERT are Generic Error Data, and are constructed as follows (see ACPI and UEFI specs for reference): * Each event begins with a Generic Error Status Block, which may contain zero or more Generic Data Entries * Each Generic Data Entry is identifiable by its Section Type field, and the data structures associated are also in the UEFI spec. * The GUIDs are listed in the Section Type field of the CPER Section Descriptor structure. BERT doesn't use this structure but simply uses its GUIDs. * Data structures used in the Generic Data Entry are named as Error Sections in the UEFI spec. * Some sections may optionally include a variable number of additional structures, e.g. an IA32/X64 processor error can report error information as well as machine contexts. It is worth noting that the Linux kernel (as of v4.4) does not attempt to parse IA32/X64 sections, and opts to hexdump them instead. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28470 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07include/cper.h: Add max of enumMarshall Dawson
Define the maximum value of the cper_x86_check_type enum, for use later in determining a legal function argument. Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28533 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07wedge100s: Add TPM supportMikolaj Walczak
Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81 Signed-off-by: Mikolaj Walczak <mwalczak@fb.com> Reviewed-on: https://review.coreboot.org/28529 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06qemu-q35: Use the TSC for udelayMichael van der Westhuizen
Use the TSC for delays on q35, ensuring that the TSC delay code is included in the correct stages when selected. Tested on qemu-35 and wedge-100s (for no regressions). Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Signed-off-by: Michael van der Westhuizen <rmikey@fb.com> Reviewed-on: https://review.coreboot.org/28526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06wedge100s: enable mrc cache in fmapOkash Khawaja
this enables mrc cache in fmap for wedge100s and always enable it in Kconfig. Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28527 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06soc/intel/cannonlake: Fix Coverity Scan reportLijian Zhao
Fix uninitialized variable OnModuleSpd, init bool with false first. BUG=CID 1395330, 1395331 TEST=N/A Change-Id: I050287370f7321ff9905937304bb3cc7f20d8c6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06mediatek: Refactor memory test code among similar SoCsTristan Shieh
Refactor memory test code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I800aa9a73f0b4588f46a98c964e2794bdf04f09d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06soc/intel/common: Add function to set BILD bit in RTCRizwan Qureshi
Add a function to set the Bios Interface Lock Down bit (bit 31) in RTC Configuration register (0x3400). This bit when set prevents the top swap enable bit (bit 0) in the RTC BUC register (0x3414) from being changed. Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06acpi/gnvs: delay setting chromeos_apci_t.vdat until depthchargeJoel Kitching
Standardize on using vboot_handoff data structure for transferring data between coreboot and depthcharge. chromeos_acpi_t.vdat is undefined until set in depthcharge. BUG=b:112288216 TEST=compile and run on eve CQ-DEPEND=CL:1198814 Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9 Signed-off-by: Joel Kitching <kitching@gmail.com> Reviewed-on: https://review.coreboot.org/28407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 06:54:01 +0000