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2015-10-22gma ACPI: Make brightness levels a per board settingNico Huber
Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22model_fxx/powernow: add dual core Socket F TDPsJonathan A. Kollasch
Values based on correlation of brand strings, brand numbers and the TDP listings on AMD's web site (Wikipedia for Athlon 64 FX-7x TDPs). Change-Id: I7e6d12d0b6cc4fefc3f84076234c62c40e08304c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10926 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
Please don't remove chipsets and mainboards without discussion and input from the owners. Someone was asking about cougar canyon 2 just a couple of weeks ago - there's obviously still interest. This reverts commit fb50124d22014742b6990a95df87a7a828e891b6. Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/12128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-20Enable MULTIPLE_CBFS_INSTANCES on x86, tooPatrick Georgi
It works there, we want it, disable that restriction. Change-Id: Idc023775f0750c980c989bff10486550e4ad1374 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/12094 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-20Revert "coreboot_table: don't add CMOS checksum twice."Nico Huber
This reverts commit e6606518243d9beda31693d40493b5f7a1a3e2e0. After some discussion on IRC we decided to revert it as libpayload can only read the copy that was removed (and other users like nvramtool can only read the other copy). So we need both copies at this time. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db Reviewed-on: http://review.coreboot.org/11696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-19vendorcode/google: Deal with MULTIPLE_CBFS_INSTANCESPatrick Georgi
We need to special-case filling out the vboot structures when we use CBFS instead of vboot's custom indexed format, otherwise (due to the way the CBFS header looks), it will try to write several million entries. Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-17armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/writePaul Kocialkowski
Some registers only allow word-sized or half-word-sized operations and will cause a data fault when accessed with byte-sized operations. However, the compiler may or may not break such an operation into smaller (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for 32 bit read/write and half-word-sized operations for 16 bit read/write. This is particularly the case on the rk3288 SRAM registers, where the watchdog tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the compiler, where a 32 bit read would be broken into byte-sized chunks, which caused a data fault when accessing the watchdog tombstone register. The definitions for byte-sized memory operations are also adapted to stay consistent with the rest. Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-17kontron/ktqm77: Tag all four USB3 ports switchable and SS capableNico Huber
With the introduction of these options in commit b26156e (bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.) the default regressed to disable these capabilities. Maybe other boards regressed too. I didn't check. Change-Id: I220896e656d00145618e61d55b74904517c7d855 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11287 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-16auron: Remove duplicate pei_data assignmentShawn Nematbakhsh
Merge artifact -- don't check spd_index twice. BUG=None TEST=Build only BRANCH=Auron Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234421 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> (cherry picked from commit 850125141b52886c845161434a1320676e59534d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05 Reviewed-on: http://review.coreboot.org/11912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-16intel/southbridge/bd82x6x: Add option to set SPI VSCC registersNico Huber
These are needed for the hardware-sequencing function of the PCH SPI interface. Values are specific to the flash chip used on a board. Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11798 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-16auron: fix can not recognize 4G memoryTim Chen
Part of the following patch was lost in the merge from chromium. This patch fixes up the spd_index for the copy from the SPD file. In spd.c "spd_index *= SPD_LEN" will change the original spd_index from gpio and let the following if(spd_index>3) to misjudge and disable channel 1 incorrectly. So we calculate the index for spd file memcpy when calling memcpy(). BUG=chrome-os-partner:32879 TEST=Can get total memory 4G on yuna 4G SKU BRANCH=Auron Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234420 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Commit-Queue: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I03f9d63623e083c99d349d938fd802d828858f70 Reviewed-on: http://review.coreboot.org/11911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Georg Wicherski <gw@oxff.net> Tested-by: build bot (Jenkins)
2015-10-16southbridge/amd/sr5650: Remove unnecessary register configurationTimothy Pearson
Do not hardcode the CPU downstream non-posted request limit; the value of this register is CPU family specific and is set appropriately in the corresponding CPU driver code. Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11935 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-16arch/x86/smbios: Add Crucial DIMM manufacturer IDTimothy Pearson
Change-Id: I975142351c0c033f9dc44670dcf819d296896921 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11934 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-10-16arch/x86/boot/smbios: Add SPD IDs for Kingston and CorsairTimothy Pearson
Change-Id: I6a32b69d3b75d7d086dc7f8ea1e195473399f406 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11933 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-10-16bootblock: Link timestamp.c only with EARLY_CBMEM_INITPaul Menzel
Commit dbeedbef (arch/x86/bootblock: Link in object files selected with bootblock-y) breaks building of x86 boards with `CONFIG_EARLY_CBMEM_INIT` *not* selected but CBMEM time stamp collection enabled. Aaron Durbin explained as below [1] and provided this patch to fix it. > That change actually processes bootblock-objs where before it never did > such a thing. I'm sure this isn’t the only issue lurking. bootblock on > x86 implied romcc and thus all the bootblock-y += rules that other > architectures use worked, but now all the implied assumptions are no > longer true on x86. > > timestamp stuff on x86 !CONFIG_EARLY_CBMEM_INIT is the issue you're > seeing. In order to compile timestamp.c for bootblock under these > conditions will mean there needs to be some more Makefile guarding. [1] http://review.coreboot.org/11864 Change-Id: I3441b9fcdbbc8bbe82b9f2075e60668a846ecf09 Fix-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-16cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFSTimothy Pearson
Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11832 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-15cpu/x86/mtrr: Add MTRR index and total MTRRs to error messagePaul Menzel
Change-Id: I626a11c17c9d05c174c507d50684e498c8604cbc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11905 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-15soc/intel/broadwell: fix USBDEBUG copy-pastaGeorg Wicherski
The broadwell soc code was upstreamed based off an old coreboot branch and apparently never tested with USBDEBUG. This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine board, as verified with a FT232H setup. The fix is simply removing outdated code that since branching off had been deduplicated in upstream coreboot, anyway. Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: http://review.coreboot.org/11874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15pcengines/apu1: Fill serial number in SMBIOSKyösti Mälkki
Serial number is derived from the MAC address of first NIC. Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11901 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-10-15pcengines/apu1: Fix CRCs in SPD fileKyösti Mälkki
Do this to wipe error message and hexdump of SPD from console log. Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11900 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15pcengines/apu1: Fix SPD for 4GB modelKyösti Mälkki
Value of tRFCmin was incorrectly using 2 Gigabit chip data. There was no observed instability or bug reports because of this. Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11899 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15ec/google: Move label to BOL to satisfy lint-testsPatrick Georgi
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11886 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15nvidia/tegra210: Drop FSF addressPatrick Georgi
Change-Id: Ia158b4c6c12fb6e22ea7fed9035574a3abedf98c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11885 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14cpu/amd/microcode: Update parser to use stock microcode blobsAudrey Pearson
The existing microcode update system used custom, manually generated microcode blob files. This made updates very difficult. Update parser to use stock microcode update files as provided by AMD. Change-Id: I772b264ad167f2a5d629dab5d64d9b0ccab3a053 Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11829 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-14skylake: ACPI: Fix compiler warnings with iasl-20150717Duncan Laurie
Updating to a new IASL introduces a lot of warnings that are not serious issues but can be fixed with some reworks. - Method local variables that are set but never used now warn, when needing to read back a register the ordering is now changed to set the value in Local0 first so the compiler does not complain. - Methods that create an object must be serialized - A ResourceTemplate declared inside a _CRS with a named variable does not seem to be able to compile without a warning. To fix this move the ResourceTemplate outside the _CRS method. - The DPTF CPU code was still using the old legacy \_PR.CPUx instead of the new \_PR.CPxx definitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=build glados with iasl-20150717 and see no warnings Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11812 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-14fsp1_1: add verstage supportAaron Durbin
In order to support verstage the cache-as-ram split is taken advantage of such that verstage has the cache-as-ram setup and rosmtage has the cache-as-ram tear down path. The verstage proper just initializes the console and attempts to run romstage which triggers the vboot verification of the firmware. In order to pass the current FSP to use during romstage a global variable in cache-as-ram is populated before returning to the assembly code which tears down cache-as-ram. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados with verstage support as well as VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage. Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11824 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-14vboot: allow more flexibility when adding verstageAaron Durbin
When a separate verstage is employed the verstage file was just being added through the cbfs-files mechanism. However, that doesn't allow one to specify other flags that aren't supported that an architecture may require. The x86 architecture is one of those entities in that it needs its verstage to be XIP. To that end provide a mechanism for adding verstage with options. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using his mechansim on x86. Change-Id: Iaba053a55a4d84d8455026e7d6fa548744edaa28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11819 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-14sandy/ivy: Fix PIRQs on ChromebooksKyösti Mälkki
This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its internal USB EHCI controller broken, with no assigned IRQ. PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive for the GPIO to use. They cannot be used for PCI devices at the same time. Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/9993 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-13t132: Add TIMESTAMP region to memlayout.ldFurquan Shaikh
If timestamps need to be enabled for t132-boards, build would break because TIMESTAMP region does not exist. With this change, t132 boards can enable "COLLECT_TIMESTAMPS" without any build error. Change-Id: I283a5ec49b5af95bd524f590e352367b7cbfd83d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-12gma ACPI: Do not overwrite backlight configurationNico Huber
Changes to CR1 and CR2 were effectively overwriting the backlight configuration from the devicetree with static values. Instead read the maximum brightness value from BCLM (backlight modulation frequency) and calculate the target level (Arg0 is the target level as percentage). Turned out that _BQC has to return a value from the list returned by _BCL. So XBQC got a little heavier to search for the correct value. Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11704 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-12gma ACPI: Consolidate non-PCH and PCH brightness levelsNico Huber
The two cases only differ in the register locations. As the values in BRIG were all the same, consolidate them. They also got normalized to percentages as the ACPI spec wants that (0x61 was 100% before). Change-Id: I9216a953bb89458ed102c39194ea370cbf463d5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11703 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-12gma: Consolidate Intel IGD ACPI code some moreNico Huber
Consolidate some common (and mostly broken) code. Will try to fix things in separate commits. Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for i945 and sch. But this needs further investigation. Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11702 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2015-10-11skylake: add support for verstageAaron Durbin
The right files just need to be added to the verstage build. Do that so a stand alone verstage builds and links. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11glados: add chromeos.c to verstageAaron Durbin
In order to build stand alone verstage the chromeos.c file needs to be part of the verstage target. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11soc/intel/common: use prog_locate() for finding fsp.binAaron Durbin
The current method was only taking the cbfs path. Because of this fsp.bin was never being utilized from the RW slots. Using prog_locate() now provides both the cbfs and vboot locate methods for free. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2b3e088326d5a965ad90806a7950b9f401ed57de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11skylake: Leave SPI controller enabledLee Leahy
Leave the SPI controller enabled upon boot block exit. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11skylake: SPI code cleanupLee Leahy
Move base address into iomap.h. Use PCI symbols instead of SPI specific symbols. Fix comments. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11vboot: prepare for x86 verstageAaron Durbin
In order to support x86 verstage proper the work buffer needs to live in cache-as-ram. However, after cache-as-ram is torn down one still needs the verification results to know which slot was selected. Though the platforms with a dedicated SRAM can just use the work buffer in SRAM, the x86 cache-as-ram platforms need a place to stash the results. For that situation cbmem is employed. This works because when cbmem is initialized cache-as-ram is still enabled. The VBOOT_DYNAMIC_WORK_BUFFER case assumes verified boot doesn't start until after cbmem is up. That doesn't change, but it's a goal to get rid of that option entirely once all other x86 platforms are moved over to pre-romstage vboot. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados with pre-romstage verification as well as VBOOT_DYNAMIC_WORK_BUFFER case. Change-Id: I7eacd0edb2b6ca52b59b74075d17c00b50676d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11821 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11cbfs: don't load x86 programs over the top of read-only mediaAaron Durbin
On x86 the early stages are currently execute-in-place which means they live in the memory-mapped spi flash. However, when loading romstage from verstage the romstage is execute-in-place so it's unnecessary to write over a read-only media -- not to mention writing to read-only memory is wrong to begin with. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Noted reduction of 20ms when loading romstage. Change-Id: I7cd399302a3925a05fbce82600b4c50ea66a0fcb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11823 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11tegra132: increase romstage size for vbootAaron Durbin
Bump up the romstage size to allow more breathing room. Change-Id: I4df7031d286c13797dccdf2f49d023bbf462fbb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11cbmem console: make verstage first class citizenAaron Durbin
The conditions in cbmem console for supporting verstage were implicitly utilizing CONFIG_BOOTBLOCK_CONSOLE to handle the cbmem console enablement. Fix it so verstage is a first class citizen for deciding actions pertaining to cbmem console. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using verstage. cbmem console shows verstage output. Change-Id: Iba79efd1c1d4056f1a105a5e10ffc95f3e69b597 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11820 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11vboot: restructure vboot work buffer handlingAaron Durbin
For the purpose of isolating the work buffer logic the surface area of the API was slimmed down. The vb2_working_data structure is no longer exposed, and the function signatures are updated accordingly. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: If64184a79e9571ee8ef9822cfce1eda20fceee00 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11818 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11vboot: remove remnants of VBOOT_STUBAaron Durbin
For vboot1 there was an rmodule that was loaded and ran to do the firmware verification. That's no longer used so remove the last vestiges of VBOOT_STUB. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I6b41544874bef4d84d0f548640114285cad3474e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11817 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin
In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11soc/intel/common: remove chipset specific callsAaron Durbin
The report_platform_info() and set_max_freq() are not being used similarly on skylake and braswell. With the addition of other SoCs I suspect a similar pattern will emerge. Instead of having weak functions to ensure things link with the hardcoded policy push these calls into their respective SoC homes. For parity, both skylake and braswell were updated to be consistent with the same calls prior to this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Built braswell. Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/303334 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel SOC common: Remove unused parametersLee Leahy
Eliminate unused parameters from the console initialization. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301204 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Braswell: Modify CB to accomodate new FSPv83Subrata Banik
Latest FSPv83 made some change related to UPD/VPD need this patch to align those BUG=None TEST=Build and Boot Cyan System BRANCH=strago-7287.B CQ-DEPEND=CL:*226897 Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291394 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303137 Original-Commit-Ready: John Zhao <john.zhao@intel.com> Original-Tested-by: John Zhao <john.zhao@intel.com> Change-Id: I9920eea84b802699454850bfde489668201ffeb6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-14 03:11:57 +0000