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2019-03-14commonlib/bubblesort: Do not try to sort less than two entriesWerner Zeh
Before start sorting check for the number of entries in the data set. If there are less than two entries, sorting makes no sense. Change-Id: Ib9d5522cdebb6559a025217f7faf318589d55a2c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-14x86/acpi: Only sort CPU IDs if more than one availableWerner Zeh
Sorting makes only sense if there are at least two entries available. Change-Id: If40638bf1fe24dcff4b7839967445fb4218184f8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-14x86/acpi: Fix Coverity issue CID 1399153Werner Zeh
This patch fixes Coverity issue CID 1399153: Uninitialized variables (UNINIT) Change-Id: I736b532c687612912271317b8941e69f41af00ba Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31782 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13mb/google/hatch: Provide DRAM part number from EEPROMFurquan Shaikh
This change reads DRAM part number from EEPROM if available and returns it using the SoC callback (mainboard_get_dram_part_number). BUG=b:127609572 TEST=Verify that DRAM part number from EEPROM is added to DMI table 17 (dmidecode -t 17). Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-13soc/intel/cannonlake: Allow mainboard to override DRAM part numberFurquan Shaikh
In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on hatch. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:127609572 Change-Id: I9b2d4c33fc378b9a24b111971ec2bfdb5f8d57d0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13src: Drop unused 'include <arch/ioapic.h>'Elyes HAOUAS
Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN()Elyes HAOUAS
Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30787 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13nb/amd/amdfam10: Remove define macro already done in 'amdfam10.h'Elyes HAOUAS
Change-Id: I69ec0eb6af67c3f12b627de2903be26252e2b35b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-13nb/amd/amdfam10: Remove 'IS_ENABLED()'Elyes HAOUAS
Change-Id: Ia1fe691e3a5fb861afb6bf7b01a9ff23ec37858f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31810 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13device/pci_ops: Rename 'where' to 'reg'Kyösti Mälkki
One could understand 'where' as bus, device, function or register. Make it clear it is register. Change-Id: I95d0330ba40510e48be70ca1d8f58aca66c8f695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-13device/pci_ops: Unify signaturesKyösti Mälkki
Use fixed width types and const pointers for dev. Change-Id: Ide3b70238479ad3e1869ed22aa4fa0f1ff8aa766 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-13sb/amd/cimx/sb800/early.c: Drop unused 'include <cbmem.h>Elyes HAOUAS
Change-Id: I0e641197119588ccf090dad2950282f54ccbd208 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31857 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13nb/intel/stage_cache.c: Drop unnecessary includesElyes HAOUAS
Change-Id: If6224c28012241e4925e05e14f0499857054f178 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-13src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS
Change-Id: I315721d6261e558c3f7145c80714262052ce0e49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31783 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS
Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeRonak Kanabar
Update header files for FSP for cometlake platform version 1065 BUG=b:125439832 Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-12drivers/intel/fsp2_0: Add provision to include PPI directorySubrata Banik
This patch adds a generic provision into FSP2.0 driver to implement dedicated PEIM to PEIM interface as per Intel FSP requirement. Change-Id: I988d55890f8dd95ccf80c1f1ec2eba8196ddf9a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-12mb/facebook/watson: Enable TPM 1.2 supportzaolin
Enable TPM 1.2 via Kconfig options and devicetree. Change-Id: I394195b3117c8583b6b506d6ad4f5170d2f45f9f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-03-11mb/google/hatch: Add Hatch_whl boardShelley Chen
Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL version of hatch so that we can rebuild the bios images for Hatch with WHL SoC. BUG=b:127310803 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_WHL is built as well. Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-11mb/google/hatch: Enable audio supportSathya Prakash M R
Following changes are done to enable audio support on hatch 1. Enable I2C4 device at 400Khz at 1.8V 2. Configure GPIO for HP INT and SPKR_PA_EN 3. Add ACPI entry for RT5682 and MAX98357A 4. Enable I2S0 and I2S1 lines 5. Enable generic max98357a driver in Kconfig BUG=b:123738217 BRANCH=none TEST=Check SSDT table for RT5682 & MAX98357a entry. Verify audio using Sound Open firmware (SOF) Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-11vendorcode/google/chromeos: Fix AMAC return typeDuncan Laurie
The r8152 kernel driver is expecting the AMAC() method to return a raw buffer, not a string. To fix this simply remove the ToString() in the return statement that was converting the buffer to a string. BUG=b:123925776 Change-Id: I7cd4244a1ccc7397d5969b817a52ea48867b4d17 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31807 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-09include/efi/efi_datatype: Convert EFI datatypes as per coreboot specificationSubrata Banik
This patch replaces commonly used EFI datatypes and structures into coreboot compatible datatypes as below: typedef UINTN efi_uintn_t Change-Id: I79cdaaa1dd63d248692989d943a15ad178c46369 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-08src/soc/intel/apollolake/cpu.c: Set up local APICMario Scheithauer
Some Apollo Lake mainboards use SeaBIOS as payload. SeaBIOS requires the initialization of the programmable interrupt controller (PIC) for faultless operation. The PIC mode is need for USB support (e.g. keyboard, memory stick) and for some Option ROMs (e.g. PXE ROM). Therefore add setup_lapic() to configure the APIC. Change-Id: I00b339ce1850729023db74da7f8845927a95dcc6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08commonlib/loglevel.h: Drop unnecessary includeElyes HAOUAS
This 'include' is only needed in console/console.h file. Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-08src/mb: Shorten 'include <arch/x86/include/arch/acpigen.h>'Elyes HAOUAS
'include <arch/acpigen.h>' is good enough. Change-Id: Idc96376571715f5dd2c386f187b5c6d1613accee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31779 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08mb/google/hatch: Create hatch_whl variantShelley Chen
In preparation for the transition of hatch from WHL to CML, we are creating a checkpoint called hatch_whl that we can use for creating firmware compatible with the WHL hatch variant. BUG=b:127310803 BRANCH=NONE TEST=NONE Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08mb/google/hatch: Initialize all gpiosShelley Chen
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07soc/intel/cannonlake: Add support for logging wake source in SMMV Sowmya
This patch adds support for logging wake source information in gsmi callbacks. With this change, all the elog logging infrastructure can be used for S0ix as well as S3 on cannonlake. BUG=b:124131938 BRANCH=none TEST=Verified that the wake events are logged during the S0ix resume: 6 | 2019-03-04 17:03:13 | S0ix Enter 7 | 2019-03-04 17:03:17 | S0ix Exit 8 | 2019-03-04 17:03:17 | Wake Source | RTC Alarm | 0 9 | 2019-03-04 17:03:55 | S0ix Enter 10 | 2019-03-04 17:03:56 | S0ix Exit 11 | 2019-03-04 17:03:56 | Wake Source | GPE # | 21 12 | 2019-03-04 17:04:36 | S0ix Enter 13 | 2019-03-04 17:04:45 | S0ix Exit 14 | 2019-03-04 17:04:45 | Wake Source | GPE # | 112 15 | 2019-03-04 17:05:01 | S0ix Enter 16 | 2019-03-04 17:05:09 | S0ix Exit 17 | 2019-03-04 17:05:09 | Wake Source | Power Button | 0 Change-Id: Id627843e22c2524dfa94395b780cf2134f386137 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-07soc/intel/cannonlake: Move power_state functions to pmutil.cV Sowmya
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. BUG=b:124131938 BRANCH=none TEST=none Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-07src/device/Kconfig: Include the discrete VGA OpROM at config UIMike Banon
Create the way of adding the discrete VGA OpROM at config UI (alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_VGA_BIOS is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-07prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if existSubrata Banik
This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=It's been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on Intel platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07arch/x86/postcar: Add separate timestamp for postcar stageSubrata Banik
This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07soc/intel/icelake: Add PM timer emulation support in ICLAamir Bohra
CPU PM TIMER EMULATION logic will help UEFI payload to execute rather wait for time tick in absence of TCO and ACPI PM timer after FSP-S. BUG=N/A TEST=Able to build and boot with tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-07mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.hElyes HAOUAS
Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07vboot: rename VB2_DISABLE_DEVELOPER_MODEJoel Kitching
Rename VB2_DISABLE_DEVELOPER_MODE to VB2_CONTEXT_DISABLE_DEVELOPER_MODE. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460645 BRANCH=none Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-07vboot: rename VB2_SD_DEV_MODE_ENABLEDJoel Kitching
Rename VB2_SD_DEV_MODE_ENABLED to VB2_SD_FLAG_DEV_MODE_ENABLED. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460644 BRANCH=none Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-07Add new CONFIG(XXX) macro to replace IS_ENABLED(CONFIG_XXX)Julius Werner
The IS_ENABLED() macro is pretty long and unwieldy for something so widely used, and often forces line breaks just for checking two Kconfigs in a row. Let's replace it with something that takes up less space to make our code more readable. From now on, if (IS_ENABLED(CONFIG_XXX)) #if IS_ENABLED(CONFIG_XXX) shall become if (CONFIG(XXX)) #if CONFIG(XXX) Change-Id: I2468427b569b974303084574125a9e1d9f6db596 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07mainboard/google/kahlee: Add additional Micron MT40A512M16TB-062E:J SPD for ↵Kevin Chiu
variants BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07soc/amd/stoneyridge: Convert SMU fanless optionsMarshall Dawson
Change the amdfwtool command line arguments to use the new --subprogram option. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: Iaae4094251974b8dad48b8d2c37bb2e43a412237 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31736 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07soc/amd/stoneyridge: Call amdfwtool with different argumentsMarshall Dawson
To prepare for consolidating amdfwtool command-line options, change the stoneyridge makefile to use the ones that will be kept. By using the new --combo-capable option, the PSP directory's pointer still appears in the correct location within the the Embedded Firmware structure. TEST=Confirm amdfw.rom file is unchanged before/after when building google/grunt BUG=b:126691068 Change-Id: Ia31ebdcb8c392d75c56811b60f1ae673f7ba79cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31730 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06soc/intel/skylake: Add H110 PCH seriesMaxim Polyakov
This patch adds support H110 chipset (Sunrise Point) for Skylake and Kaby Lake processor families by adding the corresponding IDs. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06soc/intel/skylake: Add new Northbridge and IGD IDsMaxim Polyakov
This patch adds support 1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host Bridge/DRAM Registers - 191F; 2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor https://en.wikichip.org/wiki/intel/hd_graphics/530. This is required to run coreboot on the Intel Core i5-6600 (Skylake) desktop processor. It has been tested on ASRock H110M-DVS motherboard. Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06soc/intel/braswell/include/soc/spi.h: Add OPTYPE valuesFrans Hendriks
Add SPI_OPTYPE_XXX values for the SPI controller. BUG=N/A TEST=flashrom on Facebook FBG-1701 Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-03-06soc/intel/braswell/include/soc/pci_devs.h: Add PUNIT_DEVFrans Hendriks
Intel Braswell P-UNIT is missing in pci_devs.h Add PUNIT device, function and device ID BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31711 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06mb/google/poppy/variants/nami: Use Pantheon VBTJohn Su
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 22:00:21 +0000