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2017-12-07soc/intel/apollolake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/skylake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot cannonlake rvp. Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/apollolake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/skylake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/common/block: Add Intel common Graphics controller supportSubrata Banik
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07intel/bd82x6x: Fix a small mistake in DIR_ROUTETobias Diedrich
The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07intel/bd82x6x: Add missing IRQs in ACPI PIRQ link devicesTobias Diedrich
pch_pirq_init() sets all PIRQ links to route to irq 11. However in the ACPI data, on half the links irq 11 is missing. The other half is missing irq 10. This fixes a mostly cosmetic issue in the Linux messages: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15) Change-Id: I002147d702cacf54a233196932b30732f6a433b3 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07mainboard/intel/glkrvp: Ignore Audio DMIC IOSSTATESathyanarayana Nujella
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice. So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that clock is ON in S0ix state. BUG=None TEST=put DUT in S0ix, verified DMIC_CLK in scope when wov capture path is ON Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07Revert "soc/intel/skylake: Clean up SoC ASL code."Matt DeVillier
This partially reverts commit a7b97510aeb1652fd0006c9b2d10df6568f37e2e. For the internal eMMC to be used by Windows for installation, the CARD device and _RMV methods are required. Without them, Windows does not see/show the eMMC as a valid installation target. TEST: boot google/chell with Tianocore payload and install Windows 10 to the internal eMMC drive. Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22684 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07amd/stoneyridge: Create new name/IRQ associationRichard Spiegel
Table intr_types[] is hard to maintain, and has unused spaces filled with NULL. A new table format is needed that creates strong association between the APIC register index and the associated IRQ name, is easy to maintain and has no unused space (index) to indicate that a particular register is unused while still indicating which registers are valid. Also, the string that defines the name of associated IRQ should be declared with "#define" in a header, but must be physically initiated in a source file. The "#define" must make a strong association between the used register index and the associated IRQ name. Example: #define INDEX_0X16_NAME "PerMon\t" BUG=b:69868534 TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh Processors definitions for Pci_Intr_Index. Also, check for new output format to confirm write_pci_int_table() is working as desired. There's no test for write_pci_cfg_irqs, as it's not being used by kahlee. Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07security/vboot: Remove unused include of vboot_nvstorage.hRandall Spangler
This include is not needed, and the header file is going away in vboot_reference. So, remove it. BUG=chromium:789276 BRANCH=none TEST=emerge-reef coreboot Change-Id: Ie0b37ae3d2f979f79060a15ca3f7157f49c89785 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Randall Spangler <randall@spanglers.com> Reviewed-on: https://review.coreboot.org/22733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07google/gru: Add SKU ID for ScarletJulius Werner
Scarlet has SKU detection strapping pins now. This patch adds the code to read them. BUG=b:69373077 Change-Id: I8d889a845950923bc7b5be9b79792cf3c8b6b8ad Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22697 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07rockchip/rk3399: Select GENERIC_GPIO_LIB KconfigJulius Werner
This option should've been selected by RK3399 the whole time since the SoC supports the <soc/gpio.h> interface. It wasn't really a big deal until now where I'm trying to use a the base2 read helper, though. Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22744 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/*/*/Kconfig: Remove default MMCONF_BASE_ADDRESS on Sandy BridgeArthur Heymans
Change-Id: I6f0d6d7fefc77fb05cdb629d09de8cb72496a9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-06mb/google/poppy: Remove variant_cros_gpios from variantsFurquan Shaikh
Variants nautilus and soraka currently provide the exact same definition for variant_cros_gpios as provided by the baseboard. This change removes the function defintions from variants so that the weak definition in baseboard can be used. Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22705 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy: Add config option for camera ACPI supportFurquan Shaikh
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow variants to define ACPI tables for camera support. It also prevents boards that do not need this from unnecessarily providing dummy files for camera ACPI support. Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*Furquan Shaikh
Change the prefix for TPM options from POPPY_USE_* to VARIANT_HAS_*. This makes it clear that these are variant specific options. Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*Furquan Shaikh
In order to allow variants to select different Kconfig options, this change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be selected by each variant in Kcnonfig.name. Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Remove dynamic disabling of TPMFurquan Shaikh
This change removes the dynamic disabling of TPM based on config options. Poppy and its variants will have only one type of TPM supported and so there is no need to update it dynamically. Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy/variants/soraka: Disable SPI TPMFurquan Shaikh
Soraka is no longer using SPI TPM. This change disables GSPI0 in device tree and updates gpio config accordingly. Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Disable SPI TPMFurquan Shaikh
Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in device tree and udpates gpio configuration accordingly. Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06google/kahlee: Set USB OC pinsMarc Jones
Set the USB over current pins for the Grunt baseboard and Kahlee mainboard. Removes the ACPI ASL OC code, which is not used on Stoney Ridge SOC. BUG=b:69229635 TEST=Build and boot Kahlee. Not tested with OC test fixture. Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-06soc/amd/stoneyridge: Add USB OC supportMarc Jones
Add USB overcurrent support. Adds a weak call for mainboards that don't suport USB OC. BUG=b:69229635 Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-06soc/amd/stoneyridge: Add XHCI PM register access functionsMarc Jones
Add functions to access the XHCI PM MMIO registers. Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-05google/gru: update RAMID tableLin Huang
There is some confusion with old RAMID table, make it clear, and let's no longer tangle it in future. Change-Id: I44215b4a6668074575a5df691ac1ff8fa3d15492 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-05soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh
DSX_CFG provides a config option to disable internal pull-down on AC_PRESENT. This change updates macro name to reflect this correctly. Change-Id: I620d7da4048178f86de41f3afd98543cf8efc5ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep SxFurquan Shaikh
This change updates device tree deep_sx_config to disable internal pull-down on AC_PRESENT. BUG=b:69983729 Change-Id: I041900a5262f8fd920856f126185329242a0639a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05soc/intel/skylake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh
DSX_CFG provides a config option to disable internal pull-down on AC_PRESENT. This change updates macro name to reflect this correctly. BUG=b:69983729 Change-Id: I291112858c4ce36667edf30fe303fed437baf5d2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05mb/hp/8460p: Add TPM supportBill XIE
After applying this change, /dev/tpm0 is visible inside GNU/Linux with kernel 4.9.51-1 from Debian, and there is a menu item shown inside SeaBIOS' (master only) interface if ESC is pressed. The TPM is confirmed working with [Heads](https://github.com/osresearch/heads). Change-Id: I3b845928954d203d1c3608b6704fedbd590e1fa9 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-04security/vboot: Guard google_chromeec_reboot by if clauseDaisuke Nojiri
794d222886 "cr50_enable_update: Add printk before EC hibernate" inserted printk and kicked out google_chromeec_reboot from the if-clause. This patch fixes it. BUG=none BRANCH=none TEST=none Change-Id: I058e929e2acd883d2265b2ab019743e3849cb3af Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-04amd/stoneyridge: Transfer functions from early_setup.c to southbridge.cRichard Spiegel
In preparation to deleting early_setup,c, transfer all functions except those related to wide IO to southbridge.c. BUG=b:64033893 TEST=Build and boot to OS. Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-04mb/google/fizz: Enable Wake-on-Lan featureGaggery Tsai
This patch enables WOL feature. BUG=b:69290148 BRANCH=None TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL packet. Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-03ec/lenovo/h8/acpi: Fix regression (MS Windows crash on boot)Patrick Rudolph
Fix a regression introduced by #21227 0709dc04 (ec/lenovo/h8/acpi/thermal: Add ACPI fan control). The commit caused Windows to crash as EC reads aren't allowed in the fan device or it's powerresource's methods. Implement the same approach as all other platforms using a GNVS variable named FLVL instead of reading from EC. In addition to EC reads writing to FIELD elements, in another ACPI scope, seems to be broken. Introduce a new method to set the fan disengage mode. Tested on Windows 7 and Lenovo T500. Change-Id: Ia99f8814ac14194578dcd1aa50a63e3f35c042dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-12-03sb/intel: Replace DTS2 with FLVLPatrick Rudolph
Replace the unused DTS2 field with FLVL (fan level). Required to use the fan level on all thinkpads to store and retrieve the current fan level. Possible additional use case is to modify the fan level from a SMI handler. Change-Id: I1ee5348d24b018ab1b61067813c1db63d6706c12 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22513 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-12-02google/reef: Fix whitespace inconsistency in coral codePatrick Georgi
BUG=none BRANCH=none TEST=none Change-Id: I4e61f1327027c5100773e2b837f439a939807e72 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02google/reef: add more USB tuning for coral variantsPatrick Georgi
Lava numbers are in. BUG=b:69990330 BRANCH=none TEST=verified that USB signal is within spec Change-Id: I7416ec8d058271700ebe43f8d92af61c6c0d6b42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02winbond/w83977tf: Add ACPI declarationsKeith Hui
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-02soc/intel/apollolake: Add PNP configDivya Chellap
1. Programs PNP values for AUNIT, BUNIT & TUNIT registers as per reference code. 2. A new configuration option pnp_settings is introduced in devicetree.cb to select PNP settings among performance, power, power & performance. TEST = built and booted glkrvp, verfied that the callback gets control, verified warm and cold reboots. Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02arch/riscv: Remove supervisor_trap_entryJonathan Neuschäfer
coreboot only maintains a single trap entry, because it only runs in machine mode. Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
The code dealing with the old config string isn't needed anymore, because the config string has been deprecated in favor of OpenFirmware-derived devicetrees. Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
This Supervisor Binary Interface, which is based on a page of code that's provided to operating systems by the M-mode software, has been superseded by a different (currently not really documented) SBI, which is based on directly executing ECALLs instructions. Thus some of our code becomes obsolete. Just rip it out until we implement the new SBI. Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Return from trap_handler instead of jumping outJonathan Neuschäfer
Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Unify trap returnJonathan Neuschäfer
Change-Id: I9de0c92b3f925e8f4db00d7281222a07db68b2ae Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02soc/intel/cannonlake: Initialize PMC controllerSubrata Banik
PMC controller gets hidden during FSP-Silicon initialization using sideband interface on CannonLake platform. Hence accessing PWRMBASE using PCI config space will return invalid BAR value as 0xFFFFF000. Also PMC PCI driver will not be able to initialize PMC controller as its not showing over PCI bus. coreboot PCI enumeration log shows: PCI: Static device PCI: 00:1f.2 not found, disabling it. This patch ensures PMC controller is getting initialized using boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/ BS_ON_EXIT). TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT. Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-02soc/intel/common/block: Add Intel common PMC controller support for KBL, APLSubrata Banik
SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 23:45:55 +0000